A processing core of a plurality of processing cores is configured to execute a speculative
region of code as a single atomic memory transaction with respect one or more others of the …

Systems and methods for optimizing code may use transac tional memory to optimize one
code section by forcing another code section to execute atomically. Application Source code …

5,287.483. A 2f1994 Utsumi 6,014,735 A 1/2000 Chennupaty et al. 6,023,726 A 2/2000
Saksena 6,349,361 B1 2, 2002 Altman et al. 6,523,093 B1 2/2003 Bogin et al. 7,529,895 B2 …

(57) ABSTRACT A transactional memory system coalesces two outermost transactions in a
transactional memory environment. A pro cessor of the transactional memory system …

5,657,472 A 8, 1997 Van Loo et al. 6,349,361 B1 2/2002 Altman et al. 7,185,005 B1 2/2007
Long et al. 7,516,366 B2 4/2009 Lev et al. 7,730,286 B2 6, 2010 Petersen et al. 7,890,472 …

A non-uniform memory access system includes several nodes that each have one or more
processors, caches, local main memory, and a local bus that connects a node's processor …

G06F 2/08(2006.01) A transactional memory system predicts the outcome of coa G06F
3/06(2006.01) lescing outermost memory transactions, the coalescing caus (52) US Cl ing …

Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the
discontiguous storage locations are provided by a list directly or indirectly specified by a …

A transactional memory system that utilizes indications for the coalescing of outermost
memory transactions, the coalescing causing committing of memory store data to memory for …

(57) ABSTRACT A transactional memory system predicts the outcome of coalescing
outermost memory transactions, the coalescing causing committing of memory store data to …