(57) ABSTRACT A substrate is patterned to form trenches and a semiconduc tor fin between
the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to …

Source/drain contact structures with increased contact areas for a multiple fin-based
complementary metal oxide semicon ductor field effect transistor (CMOSFET) having …

(57) ABSTRACT A semiconductor device structure is disclosed. The semicon ductor device
structure includes a mesa extending above a Substrate. The mesa has a channel region …

Nanowire channel structures of continuously stacked nanowires for complementary metal
oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS …

(57) ABSTRACT A FinFET includes a substrate, a plurality of insulators disposed on the
substrate, a gate stack and a strained material. The substrate includes at least one …

(57) ABSTRACT A semiconductor device includes at least one semiconductor fin on an
upper Surface of a base Substrate. The at least one semiconductor fin includes a strained …

Methods for fabricating integrated circuits with reduced replacement metal gate height
variability are provided. In an embodiment, a method includes providing a semiconductor …

Gate isolation methods and structures for a FinFET device leverage the definition and
formation of a gate cut opening within a sacrificial gate layer prior to patterning the sacri ficial …

A semiconductor device structure is disclosed. The semi-conductor device structure includes
a mesa extending above a substrate. The mesa has a channel region between a first side …

BACKGROUND 0001 Technical Field 0002 The present invention relates to semiconductor
devices, and more particularly to devices and methods for fabricating Such devices with …