Contextual classification with functional max-margin markov networks
We address the problem of label assignment in computer vision: given a novel 3D or 2D
scene, we wish to assign a unique label to every site (voxel, pixel, superpixel, etc.). To this …
scene, we wish to assign a unique label to every site (voxel, pixel, superpixel, etc.). To this …
The origin and implications of dark matter anisotropic cosmic infall on ≈L★ haloes
We measure the anisotropy of dark matter flows on small scales (∼ 500 kpc) in the near
environment of haloes using a large set of simulations. We rely on two different approaches …
environment of haloes using a large set of simulations. We rely on two different approaches …
[PDF][PDF] Cache design trade-offs for power and performance optimization: A case study
CL Su, AM Despain - Proceedings of the 1995 international symposium …, 1995 - dl.acm.org
Caches consume a significant amount of energy in modern microprocessors. To design an
energy-efficient microprocessor, it is important to optimize cache energy consumption. This …
energy-efficient microprocessor, it is important to optimize cache energy consumption. This …
Four-phase micropipeline latch control circuits
SB Furber, P Day - IEEE Transactions on Very Large Scale …, 1996 - ieeexplore.ieee.org
Standard micropipelines use simple two-phase control circuits. The latches employed on
AMULET1 are level sensitive, so two-to four-phase converters are required in each latch …
AMULET1 are level sensitive, so two-to four-phase converters are required in each latch …
AMULET2e: An asynchronous embedded controller
SB Furber, JD Garside, P Riocreux… - Proceedings of the …, 1999 - ieeexplore.ieee.org
AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible
asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with …
asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with …
[BUCH][B] Low-power electronics design
C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …
affecting the design of high-performance chips and portable devices. The study of power …
Single-rail handshake circuits
A Peeters, K van Berkel - Proceedings Second Working …, 1995 - ieeexplore.ieee.org
Single-rail handshake circuits are introduced as a cost effective implementation of
asynchronous circuits. Compared to double-rail implementations, the circuits are smaller …
asynchronous circuits. Compared to double-rail implementations, the circuits are smaller …
AMULET1: an asynchronous ARM microprocessor
JV Woods, P Day, SB Furber… - IEEE Transactions …, 1997 - ieeexplore.ieee.org
An asynchronous implementation of the ARM microprocessor has been developed using an
approach based on Sutherland's Micropipelines. The design allows considerable internal …
approach based on Sutherland's Micropipelines. The design allows considerable internal …
Computing without clocks: Micropipelining the ARM processor
S Furber - Asynchronous Digital Circuit Design, 1995 - Springer
High-performance VLSI microprocessors are becoming very power hungry; this presents an
increasing problem of heat removal in desk-top machines and of battery life in portable …
increasing problem of heat removal in desk-top machines and of battery life in portable …
Investigation into micropipeline latch design styles
P Day, JV Woods - IEEE Transactions on Very Large Scale …, 1995 - ieeexplore.ieee.org
An asynchronous implementation of the ARM microprocessor has been designed and
fabricated based on Sutherland's Micropipeline approach. Reviews of this work have shown …
fabricated based on Sutherland's Micropipeline approach. Reviews of this work have shown …