Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

Routing algorithms play a crucial role in the performance of Network-on-Chip (NoC)-based
Multi-Processor Systems-on-Chip (MPSoC). However, the selection of appropriate and …

Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …

As the scales of parallel applications and platforms increase the negative impact of
communication latencies on performance becomes large. Fortunately, modern High …

Network-on-chip (NoC) has become a critical shared resource in the emerging Chip
Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across …

Continuing decrease in the feature size of integrated circuits leads to increases in
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …

Three-dimensional integrated circuits (3D-ICs) offer a significant opportunity to enhance the
performance of emerging chip multiprocessors (CMPs) using high density stacked device …

We propose a reconfigurable fault-tolerant deflection routing algorithm (FTDR) based on
reinforcement learning for NoC. The algorithm reconfigures the routing table through a kind …

Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D
many-core ICs. Such networks have shorter communication hop count, compared to 2D …

Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC)
due to the increase in physical defects in advanced manufacturing processes. Two novel …