Silicon interposers enable the integration of multiple stacks of in-package memory to provide
higher bandwidth or lower energy for memory accesses. Once the interposer has been paid …

The increased computational capability in heterogeneous manycore architectures facilitates
the concurrent execution of many applications. This requires, among other things, a flexible …

Heterogeneous manycore architectures are deployed to simultaneously run multiple and
diverse applications. This requires various computing capabilities (CPUs, GPUs, and …

Ever increasing performance demand and shrinking in the transistor size together result in
complex and dense packing in large chips. That motivates designers to opt for many small …

As chip fabrication has advanced to the nano level, the increased link density has
heightened the risk of failures. The potential performance drawbacks resulting from these …

A ring topology is a common solution of network-on-chip (NoC) in industry, but is frequently
criticized to have poor scalability. In this paper, we present a novel type of multi-ring NoC …

With the rapid development of heterogeneous network-on-chip (NoC), a vast amount of
shared resources are integrated into NoC. Intense resource competition exists between …

Network-on-Chip provides scalable communication in Systems-on-Chip with many
Intellectual Property cores. Studies have shown that unutilized router buffers lead to …

Emerging applications utilize numerous Deep Neural Networks (DNNs) to address multiple
tasks simultaneously. As these applications continue to expand, there is a growing need for …

Dividing a single System-on-Chip (SoC) into multiple chiplets and integrating them via an
interposer can achieve an optimal balance between continuous transistor integration and …