Buffers in on-chip networks consume significant energy, occupy chip area, and increase
design complexity. In this paper, we make a case for a new approach to designing on-chip …

Survival capability is becoming a crucial factor in designing multicore processors built with
on-chip packet networks, or networks on chip (NoCs). In this paper, we propose a …

Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency
strongly affects the application performance on recent many-core architectures. To reduce …

Abstract Network-on-chip (NoC) is an emerging interconnect infrastructure to address the
scalability limitation of conventional shared bus architecture for many-core system-on-chip …

Nanoscale CMOS technologies are posing new network-on-chip (NoC) concepts to
gigascale system-on-chip (SoCs). However, electronic network on chip designs face several …

Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for
multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are …

Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the
interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one …

To solve the grand challenges in contemporary chip design, such as process-to-core
map**, energy reduction, and maintenance of programmer/hardware abstraction, we …

We describe the implementation of a 128× 128 crossbar switch in 90 nm CMOS standard-
cell ASIC technology. The crossbar operates at 750 MHz and is 32-bits for a port capacity …

The design of Networks-on-Chip (NoCs) components implies a wide range of techniques
and methods to address the microarchitecture of the packet-forwarding components, where …