Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

Despite recent increase in research on improvement of non-functional properties of
software, such as energy usage or program size, there is a lack of standard benchmarks for …

Modern data center applications have rapidly expanding instruction footprints that lead to
frequent instruction cache misses, increasing cost and degrading data center performance …

Fast access requirements preclude building L1 instruction caches large enough to capture
the working set of server workloads. Efforts exist to mitigate limited L1 instruction cache …

Modern data center applications have deep software stacks, with instruction footprints that
are orders of magnitude larger than typical instruction cache (I-cache) sizes. To efficiently …

While profile guided optimizations (PGO) and link time optimiza-tions (LTO) have been
widely adopted, post link optimizations (PLO) have languished until recently when …

Contemporary server workloads feature massive instruction footprints stemming from deep,
layered software stacks. The active instruction working set of the entire stack can easily …

Modern processors employ a decoupled frontend with Fetch Directed Instruction Prefetching
(FDIP) to avoid frontend stalls in data center applications. However, the large branch …

L1 instruction-cache misses pose a critical performance bottleneck in commercial server
workloads. Cache access latency constraints preclude L1 instruction caches large enough …

L1 instruction fetch misses remain a critical performance bottleneck, accounting for up to
40% slowdowns in server applications. Whereas instruction footprints typically fit within last …