In order to mitigate the impact of the growing gap between CPU speed and main memory
performance, today's computer architectures implement hierarchical memory structures. The …

The most exciting development in parallel computer architecture is the convergence of
traditionally disparate approaches on a common machine structure. This book explains the …

Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

In the past decade, advances in speed of commodity CPUs have far out-paced advances in
memory latency. Main-memory access is therefore increasingly a performance bottleneck for …

Software-controlled data prefetching offers the potential for bridging the ever-increasing
speed gap between the memory subsystem and today's high-performance processors …

Compiler writers have crafted many heuristics over the years to approximately solve NP-
hard problems efficiently. Finding a heuristic that performs well on a broad range of …

Hash join algorithms suffer from extensive CPU cache stalls. This article shows that the
standard hash join algorithm for disk-oriented databases (ie GRACE) spends over 80% of its …

In the past decade, the exponential growth in commodity CPU's speed has far outpaced
advances in memory latency. A second trend is that CPU performance advances are not …

Hardly predictable data addresses in many irregular applications have rendered prefetching
ineffective. In many cases, the only accurate way to predict these addresses is to directly …

Sparse-matrix vector multiplication is an important kernel that often runs inefficiently on
superscalar RISC processors. This paper describes techniques that increase instruction …