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Testing asynchronous circuits: A survey
H Hulgaard, SM Burns, G Borriello - Integration, 1995 - Elsevier
Asynchronous circuit design has been studied for decades, but it has only recently been
feasible to construct large and efficient asynchronous systems. The inherent differences …
feasible to construct large and efficient asynchronous systems. The inherent differences …
[کتاب][B] Asynchronous circuit design
CJ Myers - 2001 - books.google.com
With asynchronous circuit design becoming a powerful tool in the development of new
digital systems, circuit designers are expected to have asynchronous design skills and be …
digital systems, circuit designers are expected to have asynchronous design skills and be …
[کتاب][B] Logic synthesis for asynchronous controllers and interfaces
J Cortadella, M Kishinevsky, A Kondratyev, L Lavagno… - 2012 - books.google.com
This book is the result of a long friendship, of a broad international co operation, and of a
bold dream. It is the summary of work carried out by the authors, and several other wonderful …
bold dream. It is the summary of work carried out by the authors, and several other wonderful …
Automatic gate-level synthesis of speed-independent circuits
A CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND
gates and OR gates is presented. The synthesized circuits are speed-independent-that is …
gates and OR gates is presented. The synthesized circuits are speed-independent-that is …
[PDF][PDF] Basic gate implementation of speed-independent circuits
Existing methods for synthesis of speedindependent circuits under unbounded delay model
have difficulties in combining the generality of formal approach with the practicality of the …
have difficulties in combining the generality of formal approach with the practicality of the …
Automatic verification of timed circuits
This paper presents a new formalism and a new algorithm for verifying timed circuits. The
formalism, called orbital nets, allows hierarchical verification based on a behavioral …
formalism, called orbital nets, allows hierarchical verification based on a behavioral …
[کتاب][B] Computer-aided synthesis and verification of gate-level timed circuits
CJ Myers - 1996 - search.proquest.com
In recent years, there has been a resurgence of interest in the design of asynchronous
circuits due to their ability to eliminate clock skew problems, achieve average case …
circuits due to their ability to eliminate clock skew problems, achieve average case …
Towards totally self-checking delay-insensitive systems
Considers designing quasi-delay-insensitive (QDI) combinational circuits (CCs), a class of
self-timed (asynchronous) circuits. The necessity of coding both inputs and outputs of any …
self-timed (asynchronous) circuits. The necessity of coding both inputs and outputs of any …
Hazard-free implementation of speed-independent circuits
A Kondratyev, M Kishinevsky… - IEEE transactions on …, 1998 - ieeexplore.ieee.org
This paper develops a theoretical framework for the hazard-free gate-level implementation
of speed-independent circuits specified by event-based models, such as signal transition …
of speed-independent circuits specified by event-based models, such as signal transition …
Experimental results for self-dual multi-output combinational circuits
VV Saposhnikov, V Moshanin, VV Saposhnikov… - Journal of Electronic …, 1999 - Springer
In this short note, the possibilities and the limitations for the application of self-dual circuits
with alternating inputs are experimentally investigated. The original circuit is assumed to be …
with alternating inputs are experimentally investigated. The original circuit is assumed to be …