Addressing interconnect challenges for enhanced computing performance

JS Kim, J Kim, DJ Yang, J Shim, L Hu, CS Lee, J Kim… - Science, 2024 - science.org
The advancement in semiconductor technology through the integration of more devices on a
chip has reached a point where device scaling alone is no longer an efficient way to improve …

Three-dimensional transistors with two-dimensional semiconductors for future CMOS scaling

A Pal, T Chavan, J Jabbour, W Cao, K Banerjee - Nature Electronics, 2024 - nature.com
Atomically thin two-dimensional (2D) semiconductors—particularly transition metal
dichalcogenides—are potential channel materials for post-silicon complementary metal …

A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs

SK Kim, J Kim, G Choi, KW Kwon, J Jeon - IEEE Access, 2024 - ieeexplore.ieee.org
In this paper, we have investigated various middle-of-line contact architectures applied to
monolithic complementary FET inverters and have performed a comparative analysis to …

Realization of CMOS operation in 3-dimensional stacked FET with self-aligned direct backside contact

J Park, J Park, J Park, K Hwang, J Yun… - Japanese Journal of …, 2024 - iopscience.iop.org
Beyond MBCFET TM technology, the 3-dimensional stacked FET (3DSFET) emerges as a
promising contender, featuring a structure that stacks NMOS and PMOS vertically to …

3-D Self-aligned Stacked Ge Nanowires Complementary FET Featuring Single Gate S imple P rocess

YW Lin, BA Chen, KW Huang, BX Chen… - IEEE Electron …, 2024 - ieeexplore.ieee.org
In this study, we experimentally demonstrated a state-of-the-art three-dimensional (3-D) self-
aligned stacked hetero-oriented p-type Ge rectangle nanowire (NW) gate-all-around field …

Taper-Angle-Induced Variation in n/p-Stacked Versus p/n-Stacked CFET

E Jang, M Kim, C Shin - IEEE Transactions on Electron Devices, 2024 - ieeexplore.ieee.org
The complementary field-effect transistor (CFET), comprising vertically stacked gate-all-
around field-effect transistor (GAAFETs), is a promising candidate to significantly enhance …

Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock

S Choi, C Gilardi, P Gutwin, RM Radway… - arxiv preprint arxiv …, 2024 - arxiv.org
This paper presents Omni 3D-a 3D-stacked device architecture that is naturally enabled by
back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves metal layers …

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias

P Zhao, L Witters, A Jourdain, M Stucchi… - … on Electron Devices, 2024 - ieeexplore.ieee.org
Backside power delivery network (BSPDN) has gained much attention due to its potential to
independently optimize signal and power routing. In this work, long slit nano through silicon …

Hierarchical Simulation of Monolithic CFETs Using Atomistic and Continuum Models

W Choi, HK Noh, HH Park, AT Pham… - … on Simulation of …, 2024 - ieeexplore.ieee.org
We present a number of in-house TCAD capabilities that are required for the simulation and
analysis of the future logic devices, eg the complementary FET (CFET) beyond 2nm node. A …

Two-Dimensional Transition-Metal Di-Chalcogenide Devices for Chiplets

H Wakabayashi - 2024 IEEE International Meeting for Future of …, 2024 - ieeexplore.ieee.org
Two-Dimensional Transition-Metal Di-Chalcogenide Devices for Chiplets Page 1 Two-Dimensional
Transition-Metal Di-Chalcogenide Devices for Chiplets Hitoshi Wakabayashi Integrated …