Evaluation of the masked logic style MDPL on a prototype chip

T Popp, M Kirschbaum, T Zefferer… - … Hardware and Embedded …, 2007 - Springer
MDPL has been proposed as a masked logic style that counteracts DPA attacks. Recently, it
has been shown that the so-called “early propagation effect” might reduce the security of this …

BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation

M Nassar, S Bhasin, JL Danger, G Duc… - … Design, Automation & …, 2010 - ieeexplore.ieee.org
In this paper, we present BCDL (Balanced Cell-based Dual-rail Logic), a new counter-
measure against Side Channel Attacks (SCA) on cryptoprocessors implementing …

Review of gate‐level differential power analysis and fault analysis countermeasures

H Marzouqi, M Al‐Qutayri, K Salah - IET Information Security, 2014 - Wiley Online Library
Hardware implementation of modern crypto devices paves the way for a special type of
cryptanalysis, which is known as side channel analysis (SCA) attacks. These attacks are …

Side-channel attack pitfalls

K Tiri - Proceedings of the 44th annual Design Automation …, 2007 - dl.acm.org
While cryptographic algorithms are usually strong against mathematical attacks, their
practical implementation, both in software and in hardware, opens the door to side-channel …

Gate-level masking under a path-based leakage metric

AJ Leiserson, ME Marson, MA Wachs - Cryptographic Hardware and …, 2014 - Springer
Masking is a popular countermeasure against differential power analysis (DPA) and other
side-channel attacks. When designing integrated circuits to resist DPA, masking at the logic …

Design automation of real-life asynchronous devices and systems

A Taubin, J Cortadella, L Lavagno… - … and Trends® in …, 2007 - nowpublishers.com
The number of gates on a chip is quickly growing toward and beyond the one billion mark.
Kee** all the gates running at the beat of a single or a few rationally related clocks is …

TEL logic style as a countermeasure against side-channel attacks: Secure cells library in 65nm CMOS and experimental results

D Bellizia, G Scotti, A Trifiletti - IEEE Transactions on Circuits …, 2018 - ieeexplore.ieee.org
This paper presents experimental results on a dual-rail pre-charge logic family whose power
consumption is insensitive to unbalanced load conditions. The proposed logic family is …

Mitigating power-and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic

W Cilio, M Linder, C Porter, J Di, DR Thompson… - Microelectronics …, 2013 - Elsevier
Side-channel attacks have become a prevalent research topic for electronic circuits in
security-related applications, due to the strong correlation between data pattern and circuit …

Isolated WDDL: A hiding countermeasure for differential power analysis on FPGAs

RP McEvoy, CC Murphy, WP Marnane… - ACM Transactions on …, 2009 - dl.acm.org
Security protocols are frequently accelerated by implementing the underlying cryptographic
functions in reconfigurable hardware. However, unprotected hardware implementations are …

Fault injection resilience

S Guilley, L Sauvage, JL Danger… - 2010 Workshop on …, 2010 - ieeexplore.ieee.org
Fault injections constitute a major threat to the security of embedded systems. Errors
occurring in the cryptographic algorithms have been shown to be extremely dangerous …