Cosmos+ openssd: Rapid prototype for flash storage systems
J Kwak, S Lee, K Park, J Jeong, YH Song - ACM Transactions on …, 2020 - dl.acm.org
As semiconductor technology has advanced, many storage systems have begun to use non-
volatile memories as storage media. The organization and architecture of storage controllers …
volatile memories as storage media. The organization and architecture of storage controllers …
Biometric cryptosystem based on discretized fingerprint texture descriptors
This paper focuses on a biometric cryptosystem implementation and evaluation based on a
number of fingerprint texture descriptors. The texture descriptors, namely, the Gabor filter …
number of fingerprint texture descriptors. The texture descriptors, namely, the Gabor filter …
Exploring data-level error tolerance in high-performance solid-state drives
Flash storage systems have exhibited great benefits over magnetic hard drives such as low
input-output (IO) latency, and high throughput. However, NAND flash based Solid-State …
input-output (IO) latency, and high throughput. However, NAND flash based Solid-State …
Lightweight Microcontroller with Parallelized ECC-Based Code Memory Protection Unit for Robust Instruction Execution in Smart Sensors
Embedded systems typically operate in harsh environments, such as where there is external
shock, insufficient power, or an obsolete sensor after the replacement cycle. Despite these …
shock, insufficient power, or an obsolete sensor after the replacement cycle. Despite these …
Advanced bit flip concatenates BCH code demonstrates 0.93% correctable BER and faster decoding on (36 864, 32 768) emerging memories
S Ning - IEEE Transactions on Circuits and Systems I: Regular …, 2018 - ieeexplore.ieee.org
Bose-Chaudhuri-Hocquenghem (BCH) and low-density-parity-check (LDPC) are two
popular error correcting codes for non-volatile memories. However, the BCH has limited …
popular error correcting codes for non-volatile memories. However, the BCH has limited …
Improved hard-decision decoding LDPC Codec IP design
D Kim, B Chung, RE Kim - 2012 IEEE International Symposium …, 2012 - ieeexplore.ieee.org
This paper presents an area efficient low density parity check (LDPC) encoder/decoder
(Codec) implementation which can deliver high throughput performance and error correction …
(Codec) implementation which can deliver high throughput performance and error correction …
Quad-level cell NAND design and soft-bit generation for low-density parity-check decoding in system-level application
S Liu, X Zou, B Wang - Wuhan University Journal of Natural Sciences, 2018 - Springer
Abstract QLC (Quad-Level Cell) NAND flash will be one of the future technologies for next
generation memory chip after three-dimensional (3D) TLC (Triple-Level Cell) stacked NAND …
generation memory chip after three-dimensional (3D) TLC (Triple-Level Cell) stacked NAND …
[PDF][PDF] Design of Quasi-cyclic LDPC decoder for 5G NR
V SUNDARESHA - 2021 - eescholars.iitm.ac.in
With the advent of the 5th generation New Radio (5G NR) communication standard, we
expect to see massive connectivity and high data rates being delivered on batterypowered …
expect to see massive connectivity and high data rates being delivered on batterypowered …
Multi-Layer Fault Tolerance Techniques for High Reliability and Performance: Devices, Systems and Data Centers
X Xu - 2015 - search.proquest.com
In cloud computing data centers, failures may propagate quickly and widely, affecting many
physical machines and users. Particularly, soft error is one of the major sources that can …
physical machines and users. Particularly, soft error is one of the major sources that can …