A survey of recent advances in SAT-based formal verification

MR Prasad, A Biere, A Gupta - International Journal on Software Tools for …, 2005 - Springer
Dramatic improvements in SAT solver technology over the last decade and the growing
need for more efficient and scalable verification solutions have fueled research in …

The science of brute force

MJH Heule, O Kullmann - Communications of the ACM, 2017 - dl.acm.org
The science of brute force Page 1 70 COMMUNICATIONS OF THE ACM | AUGUST 2017 |
VOL. 60 | NO. 8 review articles ILL US TRA TION B Y PETER CRO W THER A SSOCIA TE S …

Nusmv 2: An opensource tool for symbolic model checking

A Cimatti, E Clarke, E Giunchiglia, F Giunchiglia… - … Aided Verification: 14th …, 2002 - Springer
This paper describes version 2 of the NuSMV tool. NuSMV is a symbolic model checker
originated from the reengineering, reimplementation and extension of SMV, the original …

Bounded model checking

A Biere - Handbook of satisfiability, 2021 - ebooks.iospress.nl
One of the most important industrial applications of SAT is currently Bounded Model
Checking (BMC). This technique is typically used for formal hardware verification in the …

Interpolation and SAT-based model checking

KL McMillan - … Aided Verification: 15th International Conference, CAV …, 2003 - Springer
We consider a fully SAT-based method of unbounded symbolic model checking based on
computing Craig interpolants. In benchmark studies using a set of large industrial circuit …

[KNIHA][B] Decision procedures

D Kroening, O Strichman - 2008 - Springer
A decision procedure is an algorithm that, given a decision problem, terminates with a
correct yes/no answer. In this book, we focus on decision procedures for decidable first …

Temporal induction by incremental SAT solving

N Eén, N Sörensson - Electronic Notes in Theoretical Computer Science, 2003 - Elsevier
We show how a very modest modification to a typical modern SAT-solver enables it to solve
a series of related SAT-instances efficiently. We apply this idea to checking safety properties …

Behavioral consistency of C and Verilog programs using bounded model checking

E Clarke, D Kroening, K Yorav - Proceedings of the 40th annual Design …, 2003 - dl.acm.org
We present an algorithm that checks behavioral consistency between an ANSI-C program
and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the …

Validating SAT solvers using an independent resolution-based checker: Practical implementations and other applications

L Zhang, S Malik - 2003 Design, Automation and Test in Europe …, 2003 - ieeexplore.ieee.org
As the use of SAT solvers as core engines in EDA applications grows, it becomes
increasingly important to validate their correctness. In this paper, we describe the …

AutoHyper: Explicit-state model checking for HyperLTL

R Beutner, B Finkbeiner - … Conference on Tools and Algorithms for the …, 2023 - Springer
HyperLTL is a temporal logic that can express hyperproperties, ie, properties that relate
multiple execution traces of a system. Such properties are becoming increasingly important …