[LIBRO][B] On-chip communication architectures: system on chip interconnect

S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Methods for evaluating and covering the design space during early design development

M Gries - Integration, 2004 - Elsevier
This paper gives an overview of methods used for design space exploration (DSE) of micro-
architectures and systems. The DSE problem generally considers two orthogonal issues:(I) …

An empirical characterization of stream programs and its implications for language and compiler design

W Thies, S Amarasinghe - … of the 19th international conference on …, 2010 - dl.acm.org
Stream programs represent an important class of high-performance computations. Defined
by their regular processing of sequences of data, stream programs appear most commonly …

Processor acceleration through automated instruction set customization

N Clark, H Zhong, S Mahlke - Proceedings. 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
Application-specific extensions to the computational capabilities of a processor provide an
efficient mechanism to meet the growing performance and power demands of embedded …

About microservices, containers and their underestimated impact on network performance

N Kratzke - arxiv preprint arxiv:1710.04049, 2017 - arxiv.org
Microservices are used to build complex applications composed of small, independent and
highly decoupled processes. Recently, microservices are often mentioned in one breath with …

Warp processors

R Lysecky, G Stitt, F Vahid - ACM Transactions on Design Automation of …, 2004 - dl.acm.org
We describe a new processing architecture, known as a warp processor, that utilizes a field-
programmable gate array (FPGA) to improve the speed and energy consumption of a …

Characterizing network processing delay

R Ramaswamy, N Weng, T Wolf - … , 2004. GLOBECOM'04., 2004 - ieeexplore.ieee.org
Computer networks have progressed from a simple store-and-forward medium to a complex
communication infrastructure. Routers in the network need to implement a variety of …

Automated custom instruction generation for domain-specific processor acceleration

NT Clark, H Zhong, SA Mahlke - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Application-specific extensions to the computational capabilities of a processor provide an
efficient mechanism to meet the growing performance and power demands of embedded …

Simulation of computer architectures: Simulators, benchmarks, methodologies, and recommendations

JJ Yi, DJ Lilja - IEEE Transactions on computers, 2006 - ieeexplore.ieee.org
Simulators have become an integral part of the computer architecture research and design
process. Since they have the advantages of cost, time, and flexibility, architects use them to …

Pagoda: Fine-grained gpu resource virtualization for narrow tasks

TT Yeh, A Sabne, P Sakdhnagool, R Eigenmann… - ACM SIGPLAN …, 2017 - dl.acm.org
Massively multithreaded GPUs achieve high throughput by running thousands of threads in
parallel. To fully utilize the hardware, workloads spawn work to the GPU in bulk by launching …