Chip design with machine learning (ML) has been widely explored to achieve better
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …

Power side-channel attacks pose a serious threat to the security of embedded devices. Most
available countermeasures have significant overheads resulting in the application not …

Gate Sizing is an important step in logic synthesis, where the cells are resized to optimize
metrics such as area, timing, power, leakage, etc. In this work, we consider the gate sizing …

A large set of ASICs uses much more transistors than its necessity, as they use a library of
cells with a limited amount of logic functions. This small number of logic functions in a …

Accurate delay analysis with distributed RC delay can be computationally expensive, and
can contribute the majority of the total runtime for gate sizers. Recent works have shown that …

We present a new approach for the cell selection problem based on a resource sharing
formulation, which is a specialization of Lagrangian relaxation with multiplicative weight …

Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event
Transient (SET) effects were considered irrelevant compared to the data rupture caused by …

Physical synthesis engines need to embrace all available parallelism to cope with the
increasing complexity of modern designs and still offer high quality of results. To achieve this …

For many years, discrete gate sizing has been widely used for timing and power optimization
in VLSI designs. The importance of gate sizing optimization has been emphasized by …

We propose techniques to achieve very fast multi-threaded gate-sizing and threshold-
voltage swap for leakage power minimization. We focus on multi-threading Lagrangian …