Architecture of computing system based on chiplet

G Shan, Y Zheng, C **ng, D Chen, G Li, Y Yang - Micromachines, 2022 - mdpi.com
Computing systems are widely used in medical diagnosis, climate prediction, autonomous
vehicles, etc. As the key part of electronics, the performance of computing systems is crucial …

Blockhammer: Preventing rowhammer at low cost by blacklisting rapidly-accessed dram rows

AG Yağlikçi, M Patel, JS Kim, R Azizi… - … Symposium on High …, 2021 - ieeexplore.ieee.org
Aggressive memory density scaling causes modern DRAM devices to suffer from
RowHammer, a phenomenon where rapidly activating (ie, hammering) a DRAM row can …

DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks

GF Oliveira, J Gómez-Luna, L Orosa, S Ghose… - IEEE …, 2021 - ieeexplore.ieee.org
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …

Evaluating STT-RAM as an energy-efficient main memory alternative

E Kültürsay, M Kandemir… - … Analysis of Systems …, 2013 - ieeexplore.ieee.org
In this paper, we explore the possibility of using STT-RAM technology to completely replace
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …

{MQSim}: A framework for enabling realistic studies of modern {Multi-Queue}{SSD} devices

A Tavakkol, J Gómez-Luna, M Sadrosadati… - … USENIX Conference on …, 2018 - usenix.org
Solid-state drives (SSDs) are used in a wide array of computer systems today, including in
datacenters and enterprise servers. As the I/O demands of these systems have increased …

Scheduling techniques for GPU architectures with processing-in-memory capabilities

A Pattnaik, X Tang, A Jog, O Kayiran… - Proceedings of the …, 2016 - dl.acm.org
Processing data in or near memory (PIM), as opposed to in conventional computational units
in a processor, can greatly alleviate the performance and energy penalties of data transfers …

The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices

JS Kim, M Patel, H Hassan… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …

Memory scaling: A systems architecture perspective

O Mutlu - 2013 5th IEEE International Memory Workshop, 2013 - ieeexplore.ieee.org
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

OWL: Cooperative thread array aware scheduling techniques for improving GPGPU performance

A Jog, O Kayiran, N Chidambaram Nachiappan… - ACM SIGPLAN …, 2013 - dl.acm.org
Emerging GPGPU architectures, along with programming models like CUDA and OpenCL,
offer a cost-effective platform for many applications by providing high thread level …

Tiered-latency DRAM: A low latency and low cost DRAM architecture

D Lee, Y Kim, V Seshadri, J Liu… - 2013 IEEE 19th …, 2013 - ieeexplore.ieee.org
The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of
increasingly large and complex computer systems. However, DRAM latency has remained …