I-GCN: A graph convolutional network accelerator with runtime locality enhancement through islandization

T Geng, C Wu, Y Zhang, C Tan, C **e, H You… - MICRO-54: 54th annual …, 2021 - dl.acm.org
Graph Convolutional Networks (GCNs) have drawn tremendous attention in the past three
years. Compared with other deep learning modalities, high-performance hardware …

Degree-quant: Quantization-aware training for graph neural networks

SA Tailor, J Fernandez-Marques, ND Lane - arxiv preprint arxiv …, 2020 - arxiv.org
Graph neural networks (GNNs) have demonstrated strong performance on a wide variety of
tasks due to their ability to model non-uniform structured data. Despite their promise, there …

Sisa: Set-centric instruction set architecture for graph mining on processing-in-memory systems

M Besta, R Kanakagiri, G Kwasniewski… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Simple graph algorithms such as PageRank have been the target of numerous hardware
accelerators. Yet, there also exist much more complex graph mining algorithms for problems …

Graphq: Scalable pim-based graph processing

Y Zhuo, C Wang, M Zhang, R Wang, D Niu… - Proceedings of the …, 2019 - dl.acm.org
Processing-In-Memory (PIM) architectures based on recent technology advances (eg,
Hybrid Memory Cube) demonstrate great potential for graph processing. However, existing …

Polygraph: Exposing the value of flexibility for graph processing accelerators

V Dadu, S Liu, T Nowatzki - 2021 ACM/IEEE 48th Annual …, 2021 - ieeexplore.ieee.org
Because of the importance of graph workloads and the limitations of CPUs/GPUs, many
graph processing accelerators have been proposed. The basic approach of prior …

Sparsep: Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures

C Giannoula, I Fernandez, JG Luna, N Koziris… - Proceedings of the …, 2022 - dl.acm.org
Several manufacturers have already started to commercialize near-bank Processing-In-
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …

Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures

C Giannoula, I Fernandez, J Gómez-Luna… - ACM SIGMETRICS …, 2022 - dl.acm.org
Several manufacturers have already started to commercialize near-bank Processing-In-
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …

Prodigy: Improving the memory latency of data-indirect irregular workloads using hardware-software co-design

N Talati, K May, A Behroozi, Y Yang… - … Symposium on High …, 2021 - ieeexplore.ieee.org
Irregular workloads are typically bottlenecked by the memory system. These workloads often
use sparse data representations, eg, compressed sparse row/column (CSR/CSC), to …

Graphpulse: An event-driven hardware accelerator for asynchronous graph processing

S Rahman, N Abu-Ghazaleh… - 2020 53rd Annual IEEE …, 2020 - ieeexplore.ieee.org
Graph processing workloads are memory intensive with irregular access patterns and large
memory footprint resulting in low data locality. Their popular software implementations …

Smash: Co-designing software compression and hardware-accelerated indexing for efficient sparse matrix operations

K Kanellopoulos, N Vijaykumar, C Giannoula… - Proceedings of the …, 2019 - dl.acm.org
Important workloads, such as machine learning and graph analytics applications, heavily
involve sparse linear algebra operations. These operations use sparse matrix compression …