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I-GCN: A graph convolutional network accelerator with runtime locality enhancement through islandization
Graph Convolutional Networks (GCNs) have drawn tremendous attention in the past three
years. Compared with other deep learning modalities, high-performance hardware …
years. Compared with other deep learning modalities, high-performance hardware …
Degree-quant: Quantization-aware training for graph neural networks
Graph neural networks (GNNs) have demonstrated strong performance on a wide variety of
tasks due to their ability to model non-uniform structured data. Despite their promise, there …
tasks due to their ability to model non-uniform structured data. Despite their promise, there …
Sisa: Set-centric instruction set architecture for graph mining on processing-in-memory systems
Simple graph algorithms such as PageRank have been the target of numerous hardware
accelerators. Yet, there also exist much more complex graph mining algorithms for problems …
accelerators. Yet, there also exist much more complex graph mining algorithms for problems …
Graphq: Scalable pim-based graph processing
Processing-In-Memory (PIM) architectures based on recent technology advances (eg,
Hybrid Memory Cube) demonstrate great potential for graph processing. However, existing …
Hybrid Memory Cube) demonstrate great potential for graph processing. However, existing …
Polygraph: Exposing the value of flexibility for graph processing accelerators
Because of the importance of graph workloads and the limitations of CPUs/GPUs, many
graph processing accelerators have been proposed. The basic approach of prior …
graph processing accelerators have been proposed. The basic approach of prior …
Sparsep: Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures
Several manufacturers have already started to commercialize near-bank Processing-In-
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …
Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures
Several manufacturers have already started to commercialize near-bank Processing-In-
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …
Prodigy: Improving the memory latency of data-indirect irregular workloads using hardware-software co-design
Irregular workloads are typically bottlenecked by the memory system. These workloads often
use sparse data representations, eg, compressed sparse row/column (CSR/CSC), to …
use sparse data representations, eg, compressed sparse row/column (CSR/CSC), to …
Graphpulse: An event-driven hardware accelerator for asynchronous graph processing
Graph processing workloads are memory intensive with irregular access patterns and large
memory footprint resulting in low data locality. Their popular software implementations …
memory footprint resulting in low data locality. Their popular software implementations …
Smash: Co-designing software compression and hardware-accelerated indexing for efficient sparse matrix operations
Important workloads, such as machine learning and graph analytics applications, heavily
involve sparse linear algebra operations. These operations use sparse matrix compression …
involve sparse linear algebra operations. These operations use sparse matrix compression …