This paper presents a near-threshold operating voltage timing error detecting 32-bit
microcontroller system. The lightweight in situ error detection and correction technique uses …

Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess
timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed …

This paper presents an innovative approach for predicting timing errors tailored to near-/sub-
threshold operations, addressing the energy-efficient requirements of digital circuits in …

Resilient circuits based on in situ timing monitoring adaptive voltage–frequency scaling
(AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) …

Specialized architecture combined with near-and subthreshold voltage circuits emerges as
a promising candidate to improve the energy efficiency in performing complex computing …

This article presents a timing slack inference and clock frequency adaption technique,
named TICA, to mitigate the large and pessimistic timing guardband reserved for process …

In order to achieve high tolerance against process, voltage, and temperature variations in
the ultralow voltage (ULV) circuits, in situ error detection and correction (EDAC) techniques …

The risk of soft errors due to radiation continues to be a significant challenge for engineers
trying to build systems that can handle harsh environments. Building systems that are …

This paper presents a methodology and chip demonstration to design near-/sub-threshold
voltage (Vt) pipelines using pulsed latches that are clocked at very wide pulses. Pulsed-latch …

Most modern computing devices make available fine-grained control of operating frequency
and voltage for power management. These interfaces, as demonstrated by recent attacks …