Synthesis and applications of III–V nanowires

E Barrigón, M Heurlin, Z Bi, B Monemar… - Chemical …, 2019 - ACS Publications
Low-dimensional semiconductor materials structures, where nanowires are needle-like one-
dimensional examples, have developed into one of the most intensely studied fields of …

Lateral InAs/Si p-type tunnel FETs integrated on Si—Part 2: Simulation study of the impact of interface traps

S Sant, K Moselund, D Cutaia, H Schmid… - … on Electron Devices, 2016 - ieeexplore.ieee.org
This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel
FET (TFET) with the same geometry as the fabricated device discussed in the first part. In …

Vertical tunneling field-effect transistor with germanium source and T-shaped silicon channel for switching and biosensing applications: A simulation study

IC Cherik, S Mohammadi - IEEE Transactions on Electron …, 2022 - ieeexplore.ieee.org
In this article, we introduce a novel vertical tunneling transistor that uses two germanium
source regions and a T-shaped silicon channel and investigate its performance for low …

Performance analysis of heterojunction tunnel FET device with variable temperature

IA Pindoo, SK Sinha, S Chander - Applied Physics A, 2021 - Springer
In this paper, the analysis of SiGe source-based heterojunction Tunnel FET device is
reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source …

Impact of trap-related non-idealities on the performance of a novel TFET-based biosensor with dual do**-less tunneling junction

IC Cherik, S Mohammadi - Scientific Reports, 2023 - nature.com
This article presents a novel dielectric-modulated biosensor based on a tunneling field-effect
transistor. It comprises a dual do**-less tunneling junction that lies above an n+ drain …

Design insights into switching performance of germanium source L-shaped gate do**less TFET based on cladding layer concept

IC Cherik, S Mohammadi - IEEE Transactions on Electron …, 2022 - ieeexplore.ieee.org
In this article, a germanium source do**less tunnel field-effect transistor (TFET) is
presented, in which the cladding layer concept is employed to induce a hole layer in the …

A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications

A Mukherjee, P Debnath, D Nirmal, M Chanda - Microelectronics Journal, 2023 - Elsevier
In this paper, the workability of a Negative Capacitance (NC)-Double Gate (DG) Tunnel FET
(NC-DGTFET) for digital logic circuit implementation has been detailed. New analytical …

Junctionless tunnel field-effect transistor with a modified auxiliary gate, a novel candidate for high-frequency applications

IC Cherik, A Abbasi, SK Maity, S Mohammadi - Micro and Nanostructures, 2023 - Elsevier
In this paper, we propose a novel junctionless tunnel field-effect transistor that uses a
tunneling gate and a modified auxiliary gate. The first one is employed to enhance the …

Impact of high-temperature and Interface traps on performance of a Junctionless tunnel FET

S Routh, D Deb, RK Baruah, R Goswami - Silicon, 2023 - Springer
Junctionless transistor (JLT) which does not have a PN junction in the source-channel-drain
path, is reported to have a lower OFF-state current and therefore is more scalable to lower …

Explaining steep-slope switching in carbon nanotube Dirac-source field-effect transistors

P Wu, J Appenzeller - IEEE Transactions on Electron Devices, 2022 - ieeexplore.ieee.org
Dirac-source field-effect transistors (DS-FETs) have been proposed as steep-slope
transistors for low-power switching. The steep-slope switching of a DS-FET originates from …