Jitter-power trade-offs in PLLs
B Razavi - IEEE Transactions on Circuits and Systems I …, 2021 - ieeexplore.ieee.org
As new applications impose jitter values in the range of a few tens of femtoseconds, the
design of phase-locked loops faces daunting challenges. This paper derives basic relations …
design of phase-locked loops faces daunting challenges. This paper derives basic relations …
A 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture
W El-Halwagy, A Nag, P Hisayasu… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its
phase noise analysis, optimization, and design for future 5G wireless transceivers. The …
phase noise analysis, optimization, and design for future 5G wireless transceivers. The …
Channel estimation and equalization for terahertz receiver with RF impairments
Z Sha, Z Wang - IEEE Journal on Selected Areas in …, 2021 - ieeexplore.ieee.org
The radio frequency (RF) impairments of analog devices have been regarded as an
important factor degrading the performance of Terahertz (THz) communications, where in …
important factor degrading the performance of Terahertz (THz) communications, where in …
A scalable 79-GHz radar platform based on single-channel transceivers
M Kucharski, A Ergintav, WA Ahmad… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
This paper presents a scalable E-band radar platform based on single-channel fully
integrated transceivers (TRX) manufactured using 130-nm silicon-germanium (SiGe) …
integrated transceivers (TRX) manufactured using 130-nm silicon-germanium (SiGe) …
A study of phase noise and frequency error of a fractional-N PLL in the course of FMCW chirp generation
A Ergintav, F Herzel, G Fischer… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper presents the theoretical and experimental results on the phase noise spectrum
and the rms frequency error of a fractional-N phase-locked loop (PLL) under frequency …
and the rms frequency error of a fractional-N phase-locked loop (PLL) under frequency …
Survey of integrated‐circuit‐oscillator phase‐noise analysis
E Pankratz, E Sánchez‐Sinencio - International Journal of …, 2014 - Wiley Online Library
This tutorial distills the salient phase‐noise analysis concepts and key equations developed
over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and …
over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and …
A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration
This paper explores a new topology of charge-pump PLL intended for ΔΣ-fractional-N
frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path …
frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path …
A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS
This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output
frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that …
frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that …
Phase noise in modular millimeter wave massive MIMO
This paper investigates the effect of oscillator phase noise on a multiuser millimeter wave
(mmWave) massive MIMO uplink as we scale up the number of base station antennas, fixing …
(mmWave) massive MIMO uplink as we scale up the number of base station antennas, fixing …
A 142-GHz 4/5 dual-modulus prescaler for wideband and low noise frequency synthesizers in 130-nm SiGe: C BiCMOS
In this contribution, the simulation and measurement results of a 4/5 dual-modulus prescaler,
operating from dc to 142 GHz with a power consumption of 144 mW, are presented. For a …
operating from dc to 142 GHz with a power consumption of 144 mW, are presented. For a …