Recent technological demand of FinFETs have been explored and reviewed in this work.
The downscaling of the conventional MOSFET urge to the researchers to innovate new …

We propose the use of a high-κ spacer to improve the electrostatic integrity and, thereby, the
scalability of silicon junctionless transistors (JLTs) for the first time. Using extensive …

Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …

This paper aims to propose a halo-doped hetero dielectric nanowire MOSFET with underlap-
extension and spacer, scaling to the sub-10 nm regime. We demonstrate that halo do** at …

Improving the on-current has been the focus of enhancing the performance of tunnel field-
effect transistors (TFETs). In this paper, we show that the increase in I_ON is not sufficient to …

FinFET is considered as the potential contender in the era of Multigate FETs. This
manuscript for the first time presents the structural variations for Junctionless FinFET devices …

In this paper, we study for the first time the impact of the design of gate sidewall spacer on
the gate-induced drain leakage (GIDL) of: 1) the conventional nanowire (NW) FETs and 2) …

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO 2 high-
spacer and compare it with its counterpart having SiO 2 low-spacer. The HfO 2 spacer …

A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel
silicon tunnel field-effect transistors (FETs) for the first time using extensive device …

In this paper, we are proposing a gate oxide stack source halo symmetric and asymmetric
underlap extension nanowire MOSFET with HfO2 spacer at 10 nm regime. The increased …