As GPU's compute capabilities grow, their memory hierarchy increasingly becomes a
bottleneck. Current GPU memory hierarchies use coarse-grained memory accesses to …

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-
1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked …

Motivated by a graphics memory system that achieves multiplied bandwidth by the number
of memories per system, HBM DRAM adopts a brand new architecture, with many technical …

The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous
standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb …

GPUs are bottlenecked by the off-chip communication bandwidth and its energy cost; hence
near-data acceleration is particularly attractive for GPUs. Integrating the accelerators within …

This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic
random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized …

Power constraints constitute a critical design issue for the portable video codec system, in
which the external dynamic random access memory (DRAM) accounts for more than half of …

Recently, the 3D stacked memory, which is known as HBM (high bandwidth memory), using
TSV process has been developed. The stacked memory structure provides increased …

Because of their widespread use in mainframes, PCs, and mobile audio and video devices,
DRAMs are being manufactured in ever increasing volume, both in stand-alone and in …

DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a
1.2 V nominal supply voltage and to be a cost-effective solution for various applications. In …