This paper presents HotSpot-a modeling methodology for develo** compact thermal
models based on the popular stacked-layer packaging scheme in modern very large-scale …

This chapter investigates in detail the actual low-level migration processes. A solid
grounding in the physics of electromigration (EM) and its specific effects on the interconnect …

The re-emerging interconnect problem is quickly becoming a major bottleneck to the
performance enhancement and cost reduction of modern digital systems. To overcome this …

We utilize Rent's rule as an empirical measure for efficient clustering and placement of
circuits in clustered Field Programmable Gate Arrays (FPGAs). We show that careful …

Throughout the past four decades, semiconductor technology has advanced at exponential
rates in both productivity and performance. In recent years, multilevel interconnect networks …

During the past decade, interconnects have replaced transistors as the dominant determiner
of chip performance. To sustain the historical rate of advance in performance, monolithic …

Because of the today's market demand for high-performance, high-density portable hand-
held applications, elec-tronic system design technology has shifted the focus from 2-D …

In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and
circuit delay minimization. We change the partitioning process itself by introducing a new …

A global net-length distribution for three-dimensional system-on-a-chip architectures is
derived to quantify the impact of the number of strata, or active layers, on the length of the …

Many design optimization methods using machine learning (ML) techniques have been
investigated to reduce the number of design iterations in the physical design flow. The …