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The policy-gradient placement and generative routing neural networks for chip design
Placement and routing are two critical yet time-consuming steps of chip design in modern
VLSI systems. Distinct from traditional heuristic solvers, this paper on one hand proposes an …
VLSI systems. Distinct from traditional heuristic solvers, this paper on one hand proposes an …
A survey of swarm intelligence techniques in VLSI routing problems
Routing is a complex and critical stage in the physical design of Very Large Scale
Integration (VLSI), minimizing interconnect length and delay to optimize overall chip …
Integration (VLSI), minimizing interconnect length and delay to optimize overall chip …
NCTU-GR 2.0: Multithreaded collision-aware global routing with bounded-length maze routing
Modern global routers employ various routing methods to improve routing speed and
quality. Maze routing is the most time-consuming process for existing global routing …
quality. Maze routing is the most time-consuming process for existing global routing …
A unified algorithm based on HTS and self-adapting PSO for the construction of octagonal and rectilinear SMT
The Steiner minimal tree (SMT) problem is an NP-hard problem, which is the best
connection model for a multi-terminal net in global routing problem. This paper presents a …
connection model for a multi-terminal net in global routing problem. This paper presents a …
Towards machine learning for placement and routing in chip design: a methodological overview
Placement and routing are two indispensable and challenging (NP-hard) tasks in modern
chip design flows. Compared with traditional solvers using heuristics or expert-well …
chip design flows. Compared with traditional solvers using heuristics or expert-well …
Timing-aware layer assignment for advanced process technologies considering via pillars
G Liu, X Zhang, W Guo, X Huang… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
Interconnect delay is a key factor that affects the chip performance in layer assignment.
Particularly in the advanced process technologies of 5 nm and beyond, interconnect delay …
Particularly in the advanced process technologies of 5 nm and beyond, interconnect delay …
A survey on Steiner tree construction and global routing for VLSI design
Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration
(VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall …
(VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall …
Efficient VLSI routing algorithm employing novel discrete PSO and multi-stage transformation
For routing industrial circuits, the Steiner minimal tree (SMT) model can be applied in
different routing problems, such as wirelength optimization, congestion reduction, and delay …
different routing problems, such as wirelength optimization, congestion reduction, and delay …
XGRouter: high-quality global router in X-architecture with particle swarm optimization
G Liu, W Guo, R Li, Y Niu, G Chen - Frontiers of Computer Science, 2015 - Springer
This paper presents a high-quality very large scale integration (VLSI) global router in X-
architecture, called XGRouter, that heavily relies on integer linear programming (ILP) …
architecture, called XGRouter, that heavily relies on integer linear programming (ILP) …
Machine learning optimal ordering in global routing problems in semiconductors
In this work, we propose a new method for ordering nets during the process of layer
assignment in global routing problems. The global routing problems that we focus on in this …
assignment in global routing problems. The global routing problems that we focus on in this …