Cohmeleon: Learning-based orchestration of accelerator coherence in heterogeneous SoCs

J Zuckerman, D Giri, J Kwon, P Mantovani… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
One of the most critical aspects of integrating loosely-coupled accelerators in
heterogeneous SoC architectures is orchestrating their interactions with the memory …

Relational memory: Native in-memory accesses on rows and columns

S Roozkhosh, D Hoornaert, JH Mun, TI Papon… - arxiv preprint arxiv …, 2021 - arxiv.org
Analytical database systems are typically designed to use a column-first data layout to
access only the desired fields. On the other hand, storing data row-first works great for …

[PDF][PDF] A memory scheduling infrastructure for multi-core systems with re-programmable logic

D Hoornaert, S Roozkhosh… - … Euromicro Conference on …, 2021 - drops.dagstuhl.de
The sharp increase in demand for performance has prompted an explosion in the complexity
of modern multi-core embedded systems. This has lead to unprecedented temporal …

The HERA methodology: reconfigurable logic in general-purpose computing

P Holzinger, M Reichenbach - IEEE Access, 2021 - ieeexplore.ieee.org
Due to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures
are inevitable to meet the increasing demand for energy efficient systems. However, one of …

Efficient traversal of decision tree ensembles with FPGAs

R Molina, F Loor, V Gil-Costa, FM Nardini… - Journal of Parallel and …, 2021 - Elsevier
Abstract System-on-Chip (SoC) based Field Programmable Gate Arrays (FPGAs) provide a
hardware acceleration technology that can be rapidly deployed and tuned, thus providing a …

CAESAR: Coherence-aided elective and seamless alternative routing via on-chip FPGA

S Roozkhosh, D Hoornaert… - 2022 IEEE Real-Time …, 2022 - ieeexplore.ieee.org
Prompted by the ever-growing demand for high-performance System-on-Chip (SoC) and the
plateauing of CPU frequencies, the SoC design landscape is shifting. In a quest to offer …

D-wash–A dynamic workload aware adaptive cache coherance protocol for multi-core processor system

V Uma, R Marimuthu - Microelectronics Journal, 2023 - Elsevier
In today's world, multi-processor plays the vital role in designing supercomputer, mobile
phones and other wearable embedded systems. To handle power and latency issues in …

Understanding and mitigating memory interference in FPGA-based HeSoCs

G Brilli, A Capotondi, P Burgio… - … Design, Automation & …, 2022 - ieeexplore.ieee.org
Like most high-end embedded systems, FPGA-based systems-on-chip (SoC) are
increasingly adopting heterogeneous designs, where CPU cores, the configurable logic and …

Hardroid: Transparent integration of crypto accelerators in android

L Piccolboni, G Di Guglielmo… - 2021 IEEE High …, 2021 - ieeexplore.ieee.org
Accelerators have become fundamental building blocks of any modern architecture.
Accelerators are often deployed on a platform by evaluating performance and energy …

Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems

E Li, S Sinha, W Zhang - … on Very Large Scale Integration (VLSI …, 2024 - ieeexplore.ieee.org
The traditional shared memory architectures (MAs) used for CPU-FPGA interaction on FPGA
system-on-chip (FPSoC) platforms lack the support for field-programmable gate array …