Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks

X Xu, B Shakya, MM Tehranipoor, D Forte - Cryptographic Hardware and …, 2017 - Springer
Logic locking has emerged as a promising technique for protecting gate-level
semiconductor intellectual property. However, recent work has shown that such gate-level …

DRiLLS: Deep reinforcement learning for logic synthesis

A Hosny, S Hashemi, M Shalan… - 2020 25th Asia and …, 2020 - ieeexplore.ieee.org
Logic synthesis requires extensive tuning of the synthesis optimization flow where the
quality of results (QoR) depends on the sequence of optimizations used. Efficient design …

Chip design with machine learning: a survey from algorithm perspective

W He, X Li, X Song, Y Hao, R Zhang, Z Du… - Science China …, 2023 - Springer
Chip design with machine learning (ML) has been widely explored to achieve better
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …

AI/ML algorithms and applications in VLSI design and technology

D Amuru, A Zahra, HV Vudumula, PK Cherupally… - Integration, 2023 - Elsevier
An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …

CAS-Lock: A security-corruptibility trade-off resilient logic locking scheme

B Shakya, X Xu, M Tehranipoor, D Forte - IACR Transactions on …, 2020 - tches.iacr.org
Logic locking has recently been proposed as a solution for protecting gatelevel
semiconductor intellectual property (IP). However, numerous attacks have been mounted on …

GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists

L Alrahis, A Sengupta, J Knechtel… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
This work introduces a generic, machine learning (ML)-based platform for functional reverse
engineering (RE) of circuits. Our proposed platform GNN-RE leverages the notion of graph …

SIMPLER MAGIC: Synthesis and map** of in-memory logic executed in a single row to improve throughput

R Ben-Hur, R Ronen, A Haj-Ali… - … on Computer-Aided …, 2019 - ieeexplore.ieee.org
In-memory processing can dramatically improve the latency and energy consumption of
computing systems by minimizing the data transfer between the memory and the processor …

The EPFL logic synthesis libraries

M Soeken, H Riener, W Haaswijk, E Testa… - arxiv preprint arxiv …, 2018 - arxiv.org
We present a collection of modular open source C++ libraries for the development of logic
synthesis applications. These libraries can be used to develop applications for the design of …

LSOracle: A logic synthesis framework driven by artificial intelligence

WL Neto, M Austin, S Temple, L Amaru… - 2019 IEEE/ACM …, 2019 - ieeexplore.ieee.org
The increasing complexity of modern Integrated Circuits (ICs) leads to systems composed of
various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such …

A classification of memory-centric computing

HAD Nguyen, J Yu, MA Lebdeh, M Taouil… - ACM Journal on …, 2020 - dl.acm.org
Technological and architectural improvements have been constantly required to sustain the
demand of faster and cheaper computers. However, CMOS down-scaling is suffering from …