Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks
Logic locking has emerged as a promising technique for protecting gate-level
semiconductor intellectual property. However, recent work has shown that such gate-level …
semiconductor intellectual property. However, recent work has shown that such gate-level …
DRiLLS: Deep reinforcement learning for logic synthesis
Logic synthesis requires extensive tuning of the synthesis optimization flow where the
quality of results (QoR) depends on the sequence of optimizations used. Efficient design …
quality of results (QoR) depends on the sequence of optimizations used. Efficient design …
Chip design with machine learning: a survey from algorithm perspective
Chip design with machine learning (ML) has been widely explored to achieve better
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …
AI/ML algorithms and applications in VLSI design and technology
An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …
development of methods to reduce the design complexity ensuing from growing process …
CAS-Lock: A security-corruptibility trade-off resilient logic locking scheme
Logic locking has recently been proposed as a solution for protecting gatelevel
semiconductor intellectual property (IP). However, numerous attacks have been mounted on …
semiconductor intellectual property (IP). However, numerous attacks have been mounted on …
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
This work introduces a generic, machine learning (ML)-based platform for functional reverse
engineering (RE) of circuits. Our proposed platform GNN-RE leverages the notion of graph …
engineering (RE) of circuits. Our proposed platform GNN-RE leverages the notion of graph …
SIMPLER MAGIC: Synthesis and map** of in-memory logic executed in a single row to improve throughput
In-memory processing can dramatically improve the latency and energy consumption of
computing systems by minimizing the data transfer between the memory and the processor …
computing systems by minimizing the data transfer between the memory and the processor …
The EPFL logic synthesis libraries
We present a collection of modular open source C++ libraries for the development of logic
synthesis applications. These libraries can be used to develop applications for the design of …
synthesis applications. These libraries can be used to develop applications for the design of …
LSOracle: A logic synthesis framework driven by artificial intelligence
The increasing complexity of modern Integrated Circuits (ICs) leads to systems composed of
various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such …
various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such …
A classification of memory-centric computing
Technological and architectural improvements have been constantly required to sustain the
demand of faster and cheaper computers. However, CMOS down-scaling is suffering from …
demand of faster and cheaper computers. However, CMOS down-scaling is suffering from …