The future transistors
The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of
complementary metal–oxide–semiconductor (CMOS) technology, represents one of the …
complementary metal–oxide–semiconductor (CMOS) technology, represents one of the …
Considerations for ultimate CMOS scaling
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
[HTML][HTML] ASAP7: A 7-nm finFET predictive process design kit
We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed
in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current …
in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current …
Process technology variation
Moore's law technology scaling has improved performance by five orders of magnitude in
the last four decades. As advanced technologies continue the pursuit of Moore's law, a …
the last four decades. As advanced technologies continue the pursuit of Moore's law, a …
Scaling challenges for advanced CMOS devices
The economic health of the semiconductor industry requires substantial scaling of chip
power, performance, and area with every new technology node that is ramped into …
power, performance, and area with every new technology node that is ramped into …
Cell circuit and layout with linear finfet structures
ST Becker - US Patent 9,563,733, 2017 - Google Patents
(57) ABSTRACT A cell circuit and corresponding layout is disclosed to include linear-
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
Power-gated 9T SRAM cell for low-energy operation
TW Oh, H Jeong, K Kang, J Park… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM)
cell that uses a read-decoupled access buffer and power-gating transistors to execute …
cell that uses a read-decoupled access buffer and power-gating transistors to execute …
Electro-thermal performance boosting in stacked Si gate-all-around nanosheet FET with engineered source/drain contacts
In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-
around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) …
around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) …
Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO2/HfO2 Gate Dielectrics
Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in 30-nm gate-
length bulk and silicon-on-insulator (SOI) FinFETs for devices with fin widths of 10-40 nm …
length bulk and silicon-on-insulator (SOI) FinFETs for devices with fin widths of 10-40 nm …
Graphene nanoribbon field-effect transistors on wafer-scale epitaxial graphene on SiC substrates
We report the realization of top-gated graphene nanoribbon field effect transistors
(GNRFETs) of∼ 10 nm width on large-area epitaxial graphene exhibiting the opening of a …
(GNRFETs) of∼ 10 nm width on large-area epitaxial graphene exhibiting the opening of a …