SEU performance of RHBD flip-flops using guard gates at 22-nm FDSOI technology node

Z Li, C Elash, J **ng, C **, L Chen… - … on Nuclear Science, 2023 - ieeexplore.ieee.org
Because of the isolation of transistors, fully depleted silicon-on-insulator (FDSOI) technology
nodes have shown better single-event upset (SEU) resilience compared with bulk …

[HTML][HTML] Efficacy of transistor interleaving in DICE flip-flops at a 22 nm FD SOI technology node

CJ Elash, Z Li, C **, L Chen, J **ng, Z Yang, S Shi - Applied Sciences, 2022 - mdpi.com
Featured Application The DICE flip-flops presented in this work show strong resistance to
single event upsets making them attractive for use in space or in environments where high …

Analysis of single-event upsets and transients in 22 nm fully depleted silicon-on-insulator logic

JV D'Amico, ST Vibbert, AC Watkins… - … on Nuclear Science, 2023 - ieeexplore.ieee.org
In this work, single-event upset (SEU) and single-event transient (SET) responses of digital
logic in a planar 22 nm conventional-well fully depleted silicon-on-insulator (FD-SOI) …

A flexible soft error mitigation framework leveraging dynamic partial reconfiguration technology

J Bai, X Wang, Z Zhao, Z Zhang, C Cai… - Microelectronics …, 2024 - Elsevier
Fault tolerance is crucial for mission-critical FPGA-based systems in radiation environments.
Soft-core processors in these systems, performing both control and computational tasks …

SEU Tolerance Efficiency of Multiple Layout-Hardened 28 nm DICE D Flip-Flops

Y Chi, C Cai, Z He, Z Wu, Y Fang, J Chen, B Liang - Electronics, 2022 - mdpi.com
Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were
designed and manufactured based on an advanced 28 nm planar technology. The …

Characterization of single event upsets of nanoscale FDSOI circuits based on the simulation and irradiation results

L Ding, C Cai, G Chen, Z Wu, J Zhang… - … on Circuits and …, 2022 - ieeexplore.ieee.org
The advanced FDSOI technology has improved performance and inherent SEU resistance
of integrated circuits, which is beneficial to the space applications. This paper provides the …

Characterization of LDO Induced Increment of SEE Sensitivity for 22-nm FDSOI SRAM

C Cai, Y Liu, M Hu, G Chen, J Yu - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The radiation sensitivity of the Static Random-Access Memory (SRAM) device depends on
the basic memory cell and peripheral circuits, and the influence of peripheral circuits is …

[HTML][HTML] SEU Hardened D Flip-Flop Design with Low Area Overhead

C Yin, Y Zhou, H Liu, Q **ang - Micromachines, 2023 - mdpi.com
D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of
an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) …

Design and Evaluation of a Radiation-Hardened FDSOI SRAM With High-Reliable Elements and Power Management Circuits for Space Application

C Cai, M Hu, L Shen, J Yu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Designing a radiation-tolerant SRAM-based system poses a significant challenge for space
facilities operating in radiation environments. Accurate evaluation of SEE sensitivity, along …

Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system

J Yu, C Cai, B Ning, S Gao, T Liu, L Xu, M Shen… - Microelectronics …, 2021 - Elsevier
This paper addresses the issue of soft error mitigation for Static Random-Access Memory
(SRAM)-based Field Programmable Gate Arrays (FPGAs) system in radiation environment to …