The re-emerging interconnect problem is quickly becoming a major bottleneck to the
performance enhancement and cost reduction of modern digital systems. To overcome this …

Throughout the past four decades, semiconductor technology has advanced at exponential
rates in both productivity and performance. In recent years, multilevel interconnect networks …

Sea of Leads (SoL) is an ultrahigh density (> 10/sup 4//cm/sup 2/) compliant chip
input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend …

Sea of leads (SoL) is a novel ultra high-density compliant wafer-level packaging technology.
SoL extends wafer-level batch processing of multilayer on-chip interconnect networks to …

Performance of a high-speed chip is largely affected by both latency and bandwidth of
global interconnects, which connect different macrocells. Therefore, one of the important …

A stochastic model for the global net-length distribution of a three-dimensional system-on-a-
chip (3D-SoC) is derived. Using the results of this model, a global interconnect design …

Designing robust power distribution network with decreasing power supply voltage and
increasing power density in given N-metal layer resources is very critical for chip …

A global interconnect design window for a three-dimensional system-on-a-chip (3D-SoC) is
established by evaluating the constraints of 1) wiring area, 2) clock wiring bandwidth, and 3) …

In this paper, we present closed form IR drop models for power distribution network in N-
metal layer system for wire-bond and flip-chip packages, given design constraints such as …

Sea of Leads (SoL) is an ultrahigh I/O density (> 10/sup 4/leads per cm/sup 2/) compliant
wafer level package (CWLP) that potentially enables terabit on/off chip electrical bandwidth …