Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

We present a survey of the state-of-the-art techniques used in performing data and memory-
related optimizations in embedded systems. The optimizations are targeted directly or …

Lower threshold voltages in deep submicron technologies cause more leakage current,
increasing static power dissipation. This trend, combined with the trend of larger/more cache …

In this paper, we address the problem of the efficient exploration of the architectural design
space for parameterized embedded systems. The exploration problem is multi-objective (eg …

ABSTRACT We introduce the Micro-Operation Cache (Uop Cache–UC) designed to reduce
processor's frontend power and energy consumption without performance degradation. The …

(57) ABSTRACT A load/store unit for a processor, and applications thereof. In an
embodiment, the load/store unit includes a load/store queue configured to store information …

In this article, we investigate compiler transformation techniques regarding the problem of
scheduling VLIW instructions aimed at reducing power consumption of VLIW architectures in …

(54) SYSTEMAND METHOD FOR PROPAGATING 5,604,909 A 2f1997 Joshi et al.
OPERANDAVAILABILITY PREDICTION 5,606,683 A 2f1997 Riordan BITS WITH …

In this paper, we propose a system-level design methodology for the efficient exploration of
the architectural parameters of the memory sub-systems, from the energy-delay joint …

Power leakage constitutes an increasing fraction of the total power consumption in modern
semiconductor technologies. Recent research efforts indicate that architectures, compilers …