Recent advances in semiconductor technology offer vertical interconnect access (via) that
extend through silicon, popularly known as through silicon via (TSV). This book provides a …

A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The
large temperatures and stress gradients can severely affect TSV delay with large variation …

This paper presents a built-in self test (BIST) methodology, architecture and circuits for
testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D …

A semianalytical model of the through-silicon via (TSV) capacitance for elevated operating
temperatures is derived and verified with electrical measurements. The effect of temperature …

3D physical design needs accurate device model of through-silicon vias (TSVs). In this
paper, physics-based electrical-thermal model is introduced for both signal and dummy …

As integrated circuits (ICs) continue to scale to smaller dimensions, relatively long
interconnects have become the dominant contributor to circuit latency and a significant …

Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the
potential for reducing the TSV capacitances and the thermal expansion stresses. This paper …

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O,
which enables smaller and thinner package sizes and cost-effective products by using wafer …

Through-silicon via (TSV)-based 3-D stacked ICs are becoming increasingly important in the
semiconductor industry, yet pre-bond testing of TSVs continues to be difficult with current …

Electrothermal effects in various through silicon via (TSV) arrays are investigated in this
paper. An equivalent lumped-element circuit model of a TSV pair is derived. The …