Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Macro placement is a critical very large-scale integration (VLSI) physical design problem
that significantly impacts the design power-performance-area (PPA) metrics. This paper …

In this invited note we describe Capo, an open-source software tool for cell placement,
mixed-size placement and floorplanning with emphasis on routability. Capo is among the …

Large macro blocks, predesigned datapaths, embedded memories, and analog blocks are
increasingly used in application-specific integrated circuit (ASIC) designs. However, robust …

Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are
increasingly used in ASIC designs. However, robust algorithms for large-scale placement of …

Reinforcement learning (RL) for physical design of silicon chips in a Google 2021 Nature
paper stirred controversy due to poorly documented claims that raised eyebrows and …

Conventional detailed placement algorithms typically assume all standard cells in the
design have the same height. However, as the complexity and design requirement increase …

We develop a projected-subgradient primal-dual Lagrange optimization for global
placement, that can be instantiated with a variety of interconnect models. It decomposes the …

In this paper, we present a new multi-packing tree (MP-tree) representation for macro
placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient …

Analytic placement methods that simultaneously minimize wire length and spread cells are
receiving renewed attention from both academia and industry. We describe the …