Electronic devices and systems, and methods for making and using the same
SE Thompson, DR Thummalapally - US Patent 8,273,617, 2012 - Google Patents
(57) ABSTRACT A suite of novel structures and methods is provided to reduce power
consumption in a wide array of electronic devices and systems. Some of these structures …
consumption in a wide array of electronic devices and systems. Some of these structures …
Transistor with threshold voltage set notch and method of fabrication thereof
R Arghavani, P Ranade, L Shifren… - US Patent …, 2014 - Google Patents
6,808 004 B2 10/2004 Kamm et a1, 7,398,497 B2 7/2008 Sato et 31. 63083994 B1 10/2004
Wang 7,402,207 B1 7/2008 Besser et a1. 6,813,750 B2 11/2004 Usami et 31 ' 7,402,872 B2 …
Wang 7,402,207 B1 7/2008 Besser et a1. 6,813,750 B2 11/2004 Usami et 31 ' 7,402,872 B2 …
Advanced Transistors with Threshold Voltage Set Dopant Structures
L Shifren, P Ranade, L Scudder - US Patent App. 12/895,785, 2011 - Google Patents
0001. This application claims the benefit of US Provi sional Application No. 61/247,300, filed
Sep. 30, 2009, the disclosure of which is incorporated by reference herein. This application …
Sep. 30, 2009, the disclosure of which is incorporated by reference herein. This application …
Electronic devices and systems, and methods for making and using the same
SE Thompson, DR Thummalapally - US Patent 8,604,530, 2013 - Google Patents
Some structures and methods to reduce power consumption in devices can be implemented
largely by reusing existing bulk CMOS process flows and manufacturing technology …
largely by reusing existing bulk CMOS process flows and manufacturing technology …
Low power semiconductor transistor structure and method of fabrication thereof
Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced
OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …
OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …
Advanced transistors with punch through suppression
L Shifren, P Ranade, PE Gregory… - US Patent …, 2013 - Google Patents
An advanced transistor with punch through suppression includes a gate with length Lg, a
well doped to have a? rst concentration of a dopant, and a screening region positioned …
well doped to have a? rst concentration of a dopant, and a screening region positioned …
Bit interleaved low voltage static random access memory (SRAM) and related methods
LT Clark - US Patent 9,070,477, 2015 - Google Patents
5,144,378 5,156,989 5,156,990 5,166,765 5,208.473 5,294,821 5,298.763 5,369,288 5,373,
186 5,384,476 5,426.328 5,444,008 5,552,332 5,559,368 5,608,253 5,622,880 5,624,863 …
186 5,384,476 5,426.328 5,444,008 5,552,332 5,559,368 5,608,253 5,622,880 5,624,863 …
Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
(65) Prior Publication Data(Continued) US 2014/O119099 A1 May 1, 2014 Primary
Examiner—Andrew Q Tran (74) Attorney, Agent, or Firm—Baker Botts LLP Related US …
Examiner—Andrew Q Tran (74) Attorney, Agent, or Firm—Baker Botts LLP Related US …
Process for manufacturing an improved analog transistor
3,958.266 A 5, 1976 Athanas 4,000,504 A 12/1976 Berger 4,021,835 A 5, 1977 Etoh et al.
4,242,691 A 12/1980 Kotani et al. 4,276.095 A 6/1981 Beilstein, Jr. et al. 4,315,781 A 2f1982 …
4,242,691 A 12/1980 Kotani et al. 4,276.095 A 6/1981 Beilstein, Jr. et al. 4,315,781 A 2f1982 …
Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of …
D Zhao, P Ranade, B McWilliams - US Patent 9,093,550, 2015 - Google Patents
(51) Int. Cl(57) ABSTRACT tion 21/8238 (2006.01) Semiconductor manufacturing processes
include forming HOIL 21/82(2006.015 conventional channel field effect transistors (FETs) …
include forming HOIL 21/82(2006.015 conventional channel field effect transistors (FETs) …