Two efficient approximate unsigned multipliers by develo** new configuration for approximate 4: 2 compressors

L Sayadi, S Timarchi… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Approximate computing is a promising approach for reducing power consumption and
design complexity in applications that accuracy is not a crucial factor. Approximate …

Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier

P Anguraj, T Krishnan - Analog Integrated Circuits and Signal Processing, 2021 - Springer
Decimal multiplication is the most common operation in arithmetic applications. This paper
presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded …

LSHIM: Low-power and Small-area Inexact Multiplier for High-speed Error-resilient Applications

A Izadi, V Jamshidi - IEEE Journal on Emerging and Selected …, 2024 - ieeexplore.ieee.org
Numerical computations in various applications can often tolerate a small degree of error. In
fields such as data mining, encoding algorithms, image processing, machine learning, and …

Improving the area of fast parallel decimal multipliers

M Véstias, H Neto - Microprocessors and Microsystems, 2018 - Elsevier
Financial and commercial applications depend on decimal arithmetic because they must
produce results that match exactly those obtained by human calculations. Decimal …

High-Performance Memory Allocation on FPGA With Reduced Internal Fragmentation

MM Sadeghi, S Timarchi, M Fazlali - IEEE Access, 2023 - ieeexplore.ieee.org
In this paper, we present two distinct hardware dynamic memory allocation schemes that are
based on the binary buddy system algorithm. Our aim is to mitigate internal fragmentation …

A new area-efficient BCD-digit multiplier

E Castillo, A Lloris, DP Morales, L Parrilla… - Digital Signal …, 2017 - Elsevier
Abstract In the Internet of Things era, with millions of devices performing financial and
commercial operations, decimal arithmetic has become very popular in the computation of …

Decimal multiplication in FPGA with a novel decimal adder/subtractor

MP Véstias, HC Neto - Algorithms, 2021 - mdpi.com
Financial and commercial data are mostly represented in decimal format. To avoid errors
introduced when converting some decimal fractions to binary, these data are processed with …

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

H Neto, M Vestias - Microprocessors and Microsystems, 2017 - Elsevier
Decimal arithmetic has recovered the attention in the field of computer arithmetic due to
decimal precision requirements of application domains like financial, commercial and …

High-speed binary coded decimal digit multipliers with multiple error detection

Z Yazdanian-Amiri, M Valinataj - Integration, 2023 - Elsevier
Decimal arithmetic in the form of binary coded decimal (BCD) numbers is preferred in many
financial, commercial and scientific applications. BCD multipliers are introduced as a key …

[HTML][HTML] Decimal multiplication using compressor based-BCD to binary converter

S Mukkamala, P Rathore, R Peesapati - Engineering science and …, 2018 - Elsevier
The objective of this work is to implement a scalable decimal to binary converter from 8 to 64
bits (ie 2-digit to 16-digit) using parallel architecture. The proposed converters, along with …