Towards globally optimal design of multipliers for FPGAs
A Böttcher, M Kumm - IEEE Transactions on Computers, 2023 - ieeexplore.ieee.org
The design of a multiplier typically consists of three steps:(1) partial product generation,(2)
compressor tree design and (3) the selection of the final adder. Conventionally, these three …
compressor tree design and (3) the selection of the final adder. Conventionally, these three …
Resource optimal design of large multipliers for FPGAs
This work presents a resource optimal approach for the design of large multipliers for
FPGAs. These are composed of smaller multipliers which can be DSP blocks or logic-based …
FPGAs. These are composed of smaller multipliers which can be DSP blocks or logic-based …
Optimizing bit-serial matrix multiplication for reconfigurable computing
Matrix-matrix multiplication is a key computational kernel for numerous applications in
science and engineering, with ample parallelism and data locality that lends itself well to …
science and engineering, with ample parallelism and data locality that lends itself well to …
Towards hardware IIR filters computing just right: Direct form I case study
Linear Time Invariant (LTI) filters are often specified and simulated using high-precision
software, before being implemented in low-precision fixed-point hardware. A problem is that …
software, before being implemented in low-precision fixed-point hardware. A problem is that …
Reconfigurable convolutional kernels for neural networks on FPGAs
Convolutional neural networks (CNNs) gained great success in machine learning
applications and much attention was paid to their acceleration on field programmable gate …
applications and much attention was paid to their acceleration on field programmable gate …