Machine learning for electronic design automation: A survey

G Huang, J Hu, Y He, J Liu, M Ma, Z Shen… - ACM Transactions on …, 2021 - dl.acm.org
With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

A survey on machine and deep learning in semiconductor industry: methods, opportunities, and challenges

AC Huang, SH Meng, TJ Huang - Cluster Computing, 2023 - Springer
The technology of big data analysis and artificial intelligence deep learning has been
actively cross-combined with various fields to increase the effect of its original low single …

Faster region-based hotspot detection

R Chen, W Zhong, H Yang, H Geng, X Zeng… - Proceedings of the 56th …, 2019 - dl.acm.org
As the circuit feature size continuously shrinks down, hotspot detection has become a more
challenging problem in modern DFM flows. Developed deep learning techniques have …

Deep H-GCN: Fast analog IC aging-induced degradation estimation

T Chen, Q Sun, C Zhan, C Liu, H Yu… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
With continued scaling, the transistor aging induced by hot carrier injection (HCI) and bias
temperature instability (BTI) causes an increasing failure of nanometer-scale integrated …

When wafer failure pattern classification meets few-shot learning and self-supervised learning

H Geng, F Yang, X Zeng, B Yu - 2021 IEEE/ACM International …, 2021 - ieeexplore.ieee.org
Due to advances in semiconductor processing technologies, wafer failure pattern detection
plays a key role in preventing yield loss excursion events for semiconductor manufacturing …

High-speed adder design space exploration via graph neural processes

H Geng, Y Ma, Q Xu, J Miao, S Roy… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Adders are the primary components in the data-path logic of a microprocessor, and thus,
adder design has been always a critical issue in the very large-scale integration (VLSI) …

Machine learning in advanced IC design: A methodological survey

T Chen, GL Zhang, B Yu, B Li… - IEEE Design & …, 2022 - ieeexplore.ieee.org
The increasing complexity and size of design space poses significant challenges for
integrated circuit (IC) design. This article discusses the potential of machine learning (ML) …

Efficient ilt via multi-level lithography simulation

S Sun, F Yang, B Yu, L Shang… - 2023 60th ACM/IEEE …, 2023 - ieeexplore.ieee.org
Inverse Lithography Technology (ILT) is a widely investigated method to improve the yield of
chip manufacturing. However, high computational complexity and difficulty in fabricating …

An efficient sharing grouped convolution via bayesian learning

T Chen, B Duan, Q Sun, M Zhang, G Li… - … on Neural Networks …, 2021 - ieeexplore.ieee.org
Compared with traditional convolutions, grouped convolutional neural networks are
promising for both model performance and network parameters. However, existing models …

Doomed run prediction in physical design by exploiting sequential flow and graph learning

YC Lu, S Nath, V Khandelwal… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Modern designs are increasingly reliant on physical design (PD) tools to derive full
technology scaling benefits of Moore's Law. Designers often perform power, performance …