Scaling challenges for advanced CMOS devices
The economic health of the semiconductor industry requires substantial scaling of chip
power, performance, and area with every new technology node that is ramped into …
power, performance, and area with every new technology node that is ramped into …
Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates
An efficient technique for designing high‐performance logic circuits operating in sub‐
threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change …
threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change …
Semiconductor radio frequency switch with body contact
M Carroll, DC Kerr, CR Iversen, P Mason… - US Patent …, 2014 - Google Patents
3,699,359 A 10/1972 Shelby 3,975,671 A 8, 1976 Stoll 3,988,727 A 10, 1976 Scott
4,244,000 A 1/1981 Ueda et al. 4,256,977 A 3, 1981 Hendrickson 4,316,101 A 2f1982 …
4,244,000 A 1/1981 Ueda et al. 4,256,977 A 3, 1981 Hendrickson 4,316,101 A 2f1982 …
Modelling of the dynamic threshold MOSFET
A Jiménez-P, FJ De la Hidalga-W, MJ Deen - IEE Proceedings-Circuits, Devices …, 2005 - IET
Despite the inappropriateness of the depletion approximation when the source-substrate
junction is slightly forward biased, conventional SPICE models are being used to simulate …
junction is slightly forward biased, conventional SPICE models are being used to simulate …
[PDF][PDF] A novel ultra-low-energy bulk dynamic threshold inverter scheme
In this paper we propose the use of a new DTMOS scheme in sub-threshold inverters. The
results indicate that this scheme can provide better power efficiency than standard sub …
results indicate that this scheme can provide better power efficiency than standard sub …
Variable threshold MOSFET approach (through dynamic threshold MOSFET) for universal logic gates
K Ragini, M Satyam, BC **aga - arxiv preprint arxiv:1003.6030, 2010 - arxiv.org
In this article, we proposed a Variable threshold MOSFET (VTMOS) approach which is
realized from Dynamic Threshold MOSFET (DTMOS), suitable for sub-threshold digital …
realized from Dynamic Threshold MOSFET (DTMOS), suitable for sub-threshold digital …
Low leakage and minimum energy consumption in CMOS logic circuits
R Lorenzo, S Chaudhary - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
This paper presents a novel design to reduce sub threshold leakage current. The leakage
controlled transistors are utilized to change dynamically the ground voltage level which is …
controlled transistors are utilized to change dynamically the ground voltage level which is …
Low-power 7.2 GHz complementary all-N-transistor logic using 90 nm CMOS technology
CH Hsu, GN Sung, TY Yao, CY Juan… - … on Circuits and …, 2009 - ieeexplore.ieee.org
This paper proposed an complementary all-N-transistor (CANT) comprising ANT logic and
inverted ANT logic. In ANT logic's N-Block, the threshold voltage of the transistors is variable …
inverted ANT logic. In ANT logic's N-Block, the threshold voltage of the transistors is variable …
Analysis of the threshold voltage BSIM-model for a short channel PD-SOI DTMOS
A Jimenez-P - … 4th International Conference on Electrical and …, 2007 - ieeexplore.ieee.org
The threshold voltage is a fundamental parameter necessary to predict the correct behavior
of circuits based on Dynamic Threshold MOSFETs. In this work, we analyzed the short …
of circuits based on Dynamic Threshold MOSFETs. In this work, we analyzed the short …
A 32-bit carry lookahead adder design using complementary all-N-transistor logic
GN Sung, CY Juan, CC Wang - 2008 15th IEEE International …, 2008 - ieeexplore.ieee.org
A complementary all-N-transistor (CANT) comprising the ANT logic and a novel inverted
ANT logic is proposed in this paper. The threshold voltage of the transistors in the ANT …
ANT logic is proposed in this paper. The threshold voltage of the transistors in the ANT …