Testing with model checkers: a survey

G Fraser, F Wotawa, PE Ammann - … Testing, Verification and …, 2009 - Wiley Online Library
About a decade after the initial proposal to use model checkers for the generation of test
cases we take a look at the results in this field of research. Model checkers are formal …

[BOOK][B] Processor description languages

P Mishra, N Dutt - 2011 - books.google.com
Efficient design of embedded processors plays a critical role in embedded systems design.
Processor description languages and their associated specification, exploration and rapid …

Automated test generation for activation of assertions in RTL models

Y Lyu, P Mishra - 2020 25th Asia and South Pacific Design …, 2020 - ieeexplore.ieee.org
A major challenge in assertion-based validation is how to activate the assertions to ensure
that they are valid. While existing test generation using model checking is promising, it …

Systematic software-based self-test for pipelined processors

D Gizopoulos, M Psarakis, M Hatzimihail… - … Transactions on Very …, 2008 - ieeexplore.ieee.org
Software-based self-test (SBST) has recently emerged as an effective methodology for the
manufacturing test of processors and other components in systems-on-chip (SoCs). By …

Directed test generation for activation of security assertions in rtl models

H Witharana, Y Lyu, P Mishra - ACM Transactions on Design Automation …, 2021 - dl.acm.org
Assertions are widely used for functional validation as well as coverage analysis for both
software and hardware designs. Assertions enable runtime error detection as well as faster …

Directed test generation for validation of cache coherence protocols

Y Lyu, X Qin, M Chen, P Mishra - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Computing systems utilize multicore processors with complex cache coherence protocols to
meet the increasing need for performance and energy improvement. It is a major challenge …

Architecture description languages for programmable embedded systems

P Mishra, N Dutt - IEE proceedings-computers and digital techniques, 2005 - IET
Embedded systems present a tremendous opportunity to customise designs by exploiting
the application behaviour. Shrinking time-to-market, coupled with short product lifetimes …

Functional coverage driven test generation for validation of pipelined processors

P Mishra, N Dutt - Design, Automation and Test in Europe, 2005 - ieeexplore.ieee.org
Functional verification of microprocessors is one of the most complex and expensive tasks in
the current system-on-chip design process. A significant bottleneck in the validation of such …

Specification-driven directed test generation for validation of pipelined processors

P Mishra, N Dutt - ACM Transactions on Design Automation of Electronic …, 2008 - dl.acm.org
Functional validation is a major bottleneck in pipelined processor design due to the
combined effects of increasing design complexity and lack of efficient techniques for directed …

Functional test generation using design and property decomposition techniques

HM Koo, P Mishra - ACM Transactions on Embedded Computing …, 2009 - dl.acm.org
Functional verification of microprocessors is one of the most complex and expensive tasks in
the current system-on-chip design methodology. Simulation using functional test vectors is …