Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
Multirate timestamp modeling for ultralow-jitter frequency synthesis: A tutorial
Y Hu, T Siriburanon… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this tutorial brief, we introduce a unified wideband phase-noise theory framework of
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
A 30-GHz class-F quadrature DCO using phase shifts between drain–gate–source for low flicker phase noise and I/Q exactness
In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary–Secondary S-PD Measuring 39.6-fsRMS Jitter, −260.2-dB FOM, and −70.96–dBc …
This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We
innovate a fully-passive sampling phase detector with passive-gain multiplication after the …
innovate a fully-passive sampling phase detector with passive-gain multiplication after the …
An Ultra-Low-Jitter Fast-Hop** Fractional-N PLL With LC DTC and Hybrid-Proportional Paths
This work presents an ultra-low-jitter fractional-N PLL capable of wideband fast hop**.
There is an analog proportional path and a digital proportional/integral path in the PLL. The …
There is an analog proportional path and a digital proportional/integral path in the PLL. The …
Analysis and design of a 15.2-to-18.2-GHz inverse-class-F VCO with a balanced dual-core topology suppressing the flicker noise upconversion
This paper presents the theory and implementation of a balanced dual-core inverse-class-F
(class-F) voltage-controlled oscillator (VCO). The class-F topology supports high-quality …
(class-F) voltage-controlled oscillator (VCO). The class-F topology supports high-quality …
A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With 5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing
A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this
article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of …
article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of …
A Multi-Core Series-Resonance CMOS Oscillator
Multi-core and series-resonance (SR) techniques have been proposed to achieve ultra-low
phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed …
phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed …
[HTML][HTML] Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art
This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation
Y Hu, W Tao, RB Staszewski - IEEE Open Journal of the Solid …, 2024 - ieeexplore.ieee.org
A fractional-N frequency synthesizer with low total jitter [eg,< 50fsrms, accounting for both
phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high …
phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high …