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An 8K H. 265/HEVC video decoder chip with a new system pipeline design
8K ultra-HD is being promoted as the next-generation video specification. While the High
Efficiency Video Coding (HEVC) standard greatly enhances the feasibility of 8K with a …
Efficiency Video Coding (HEVC) standard greatly enhances the feasibility of 8K with a …
Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
A unified architecture for fast and efficient computation of the set of two-dimensional (2-D)
transforms adopted by the most recent state-of-the-art digital video standards is presented in …
transforms adopted by the most recent state-of-the-art digital video standards is presented in …
Scalable integer DCT architecture for HEVC encoder
HEVC (H. 265) standard was proposed as a means to increase the compression rate with no
loss in video quality. Large integer DCT, with sizes 16x16 and 32x32, is one of the key new …
loss in video quality. Large integer DCT, with sizes 16x16 and 32x32, is one of the key new …
A low-cost VLSI architecture of multiple-size IDCT for H. 265/HEVC
In this paper, we present an area-efficient 4/8/16/32-point inverse discrete cosine transform
(IDCT) architecture for a HEVC decoder. Compared with previous work, this work reduces …
(IDCT) architecture for a HEVC decoder. Compared with previous work, this work reduces …
Real‐time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding
In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger
integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the …
integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the …
A low-power VLSI architecture for HEVC de-quantization and inverse transform
In this paper, we present a low-power system for the de-quantization and inverse transform
of HEVC. Firstly, we present a low-delay circuit to process the coded results of the syntax …
of HEVC. Firstly, we present a low-delay circuit to process the coded results of the syntax …
[PDF][PDF] REGISTER TRANSFER LEVEL DESIGN OF TRANSPOSE MEMORY FOR THE TWO-DIMENSIONINVERSE DISCRETE COSINE TRANSFORM FOR HIGH …
G JIANN - 2018 - eprints.utm.my
The rapid revolution in consumer devices have caused in a variety of emerging video coding
applications which contribute the aggressive demands on video compression requirement …
applications which contribute the aggressive demands on video compression requirement …
[PDF][PDF] Fast Algorithm and VLSI Architecture of HEVC Mode Decision and Reconstruction Loop Based on Data Reuse and Reordering
SUN Heming - 2017 - core.ac.uk
With the development of the information society, multimedia contents are widely used. Video
data occupies the majority of multimedia data and it will dramatically grow when high …
data occupies the majority of multimedia data and it will dramatically grow when high …
[PDF][PDF] Fast Algorithm and VLSI Architecture of HEVC Mode Decision and Reconstruction Loop Based on Data Reuse and Reordering
孫鶴鳴 - 2016 - waseda.repo.nii.ac.jp
With the development of the information society, multimedia contents are widely used. Video
data occupies the majority of multimedia data and it will dramatically grow when high …
data occupies the majority of multimedia data and it will dramatically grow when high …
[PDF][PDF] A Study on Hardware Architecture for H. 265/HEVC Fast Mode Decision and Transform
趙文軍， チョウブングン - 2015 - ir.library.osaka-u.ac.jp
This thesis mainly discusses the fast mode decision algorithms for the H. 265/HEVC (high
efficiency video coding). HEVC has incorporated a series of the state-of-the-art technologies …
efficiency video coding). HEVC has incorporated a series of the state-of-the-art technologies …