Strained-semiconductor-on-insulator device structures
TA Langdo, MT Currie, R Hammond… - US Patent …, 2006 - Google Patents
US6995430B2 - Strained-semiconductor-on-insulator device structures - Google Patents
US6995430B2 - Strained-semiconductor-on-insulator device structures - Google Patents …
US6995430B2 - Strained-semiconductor-on-insulator device structures - Google Patents …
Methods of forming strained-semiconductor-on-insulator finFET device structures
AJ Lochtefeld, TA Langdo, R Hammond… - US Patent …, 2006 - Google Patents
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Hybrid fin field-effect transistor structures and related methods
MT Currie - US Patent 8,183,627, 2012 - Google Patents
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5.426, 316 5.439, 843 5,442,205 5,461,243 5,461,250 5,462,883 5,476,813 5,479,033 …
CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same
GJ Bae, TH Choe, SS Kim, HS Rhee, N Lee… - US Patent …, 2005 - Google Patents
(57) ABSTRACT CMOS integrated circuit devices include an electrically insulating layer and
an unstrained Silicon active layer on the electrically insulating layer. An insulated gate …
an unstrained Silicon active layer on the electrically insulating layer. An insulated gate …
Semiconductor device
N Sugiyama, T Tezuka, T Mizuno, S Takagi - US Patent 6,774,390, 2004 - Google Patents
Semiconductor board formed on a Selected portion of the insulating layer, a Semiconductor
layer formed on at least one of the major Side Surfaces of the Semiconductor board, which is …
layer formed on at least one of the major Side Surfaces of the Semiconductor board, which is …
Control of strain in device layers by prevention of relaxation
MT Currie - US Patent 7,335,545, 2008 - Google Patents
US7335545B2 - Control of strain in device layers by prevention of relaxation - Google Patents
US7335545B2 - Control of strain in device layers by prevention of relaxation - Google Patents …
US7335545B2 - Control of strain in device layers by prevention of relaxation - Google Patents …
Method of selective removal of SiGe alloys
R Hammond, M Currie - US Patent 6,900,094, 2005 - Google Patents
(57) ABSTRACT A method is disclosed of forming buried channel devices and Surface
channel devices on a heterostructure Semicon ductor Substrate. In an embodiment, the …
channel devices on a heterostructure Semicon ductor Substrate. In an embodiment, the …
Control of strain in device layers by selective relaxation
MT Currie - US Patent 7,307,273, 2007 - Google Patents
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Buried channel strained silicon FET using a supply layer created through ion implantation
EA Fitzgerald - US Patent 6,555,839, 2003 - Google Patents
US PATENT DOCUMENTS A circuit including at least one strained channel, enhance'' ment
mode PET, and at least one strained channel, depletion 4,710,788 A 12/1987 Dambkes et …
mode PET, and at least one strained channel, depletion 4,710,788 A 12/1987 Dambkes et …
RF circuits including transistors having strained material layers
G Braithwaite, R Hammond, M Currie - US Patent 7,709,828, 2010 - Google Patents
(52) US Cl................... 257/24; 257/219; 257/E29. 012 (58) Field of Classification
Search.................... 257/24 See application file for complete search history. Circuits for …
Search.................... 257/24 See application file for complete search history. Circuits for …