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Programmable resistive device and memory using diode as selector
SC Chung - US Patent 9,818,478, 2017 - Google Patents
Building programmable resistive devices in contact holes at the crossover of a plurality of
conductor lines in more than two vertical layers is disclosed. There are plurality of first …
conductor lines in more than two vertical layers is disclosed. There are plurality of first …
Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
P Bauser - US Patent 7,499,358, 2009 - Google Patents
(54) METHOD AND CIRCUITRY TO GENERATE A 4,032.947 A 6, 1977 Kesel et al.
REFERENCE CURRENT FOR READING A 4,250,569 A 2, 1981 Sasaki et al. MEMORY …
REFERENCE CURRENT FOR READING A 4,250,569 A 2, 1981 Sasaki et al. MEMORY …
Memory cells, memory cell arrays, methods of using and methods of making
Y Widjaja - US Patent 9,715,932, 2017 - Google Patents
(57) ABSTRACT A semiconductor memory cell and arrays of memory cells are provided In at
least one embodiment, a memory cell includes a Substrate having a top Surface, the …
least one embodiment, a memory cell includes a Substrate having a top Surface, the …
Memory cells, memory cell arrays, methods of using and methods of making
Y Widjaja - US Patent 9,847,131, 2017 - Google Patents
(57) ABSTRACT A semiconductor memory cell and arrays of memory cells are provided In at
least one embodiment, a memory cell includes a substrate having a top surface, the …
least one embodiment, a memory cell includes a substrate having a top surface, the …
Memory cells, memory cell arrays, methods of using and methods of making
Y Widjaja - US Patent 9,978,450, 2018 - Google Patents
(57) ABSTRACT A semiconductor memory cell and arrays of memory cells are provided In at
least one embodiment, a memory cell includes a substrate having a top surface, the …
least one embodiment, a memory cell includes a substrate having a top surface, the …
Circuit and system of using FinFET for building programmable resistive devices
SC Chung - US Patent 8,848,423, 2014 - Google Patents
FET technologies can be used as program selectors or One Time Programmable (OTP)
element in a programmable resis tive device. Such as interconnect fuse, contact/via fuse …
element in a programmable resis tive device. Such as interconnect fuse, contact/via fuse …
Memory cells, memory cell arrays, methods of using and methods of making
Y Widjaja - US Patent 10,109,349, 2018 - Google Patents
(57) ABSTRACT A semiconductor memory cell and arrays of memory cells are provided In at
least one embodiment, a memory cell includes a substrate having a top surface, the …
least one embodiment, a memory cell includes a substrate having a top surface, the …
Memory cells, memory cell arrays, methods of using and methods of making
Y Widjaja - US Patent 10,403,361, 2019 - Google Patents
(57) ABSTRACT A semiconductor memory cell and arrays of memory cells are provided In at
least one embodiment, a memory cell includes a substrate having a top surface, the …
least one embodiment, a memory cell includes a substrate having a top surface, the …
Memory cells, memory cell arrays, methods of using and methods of making
Y Widjaja - US Patent 10,242,739, 2019 - Google Patents
(57) ABSTRACT A semiconductor memory cell and arrays of memory cells are provided In at
least one embodiment, a memory cell includes a substrate having a top surface, the …
least one embodiment, a memory cell includes a substrate having a top surface, the …
Memory cells, memory cell arrays, methods of using and methods of making
Y Widjaja - US Patent 10,553,281, 2020 - Google Patents
(57) ABSTRACT A semiconductor memory cell and arrays of memory cells are provided In at
least one embodiment, a memory cell includes a substrate having a top surface, the …
least one embodiment, a memory cell includes a substrate having a top surface, the …