Intelligent hotspot prediction for network-on-chip-based multicore systems
Hotspots are network-on-chip (NoC) routers or modules in multicore systems which
occasionally receive packetized data from other networked element producers at a rate …
occasionally receive packetized data from other networked element producers at a rate …
A holistic approach towards intelligent hotspot prevention in network-on-chip-based multicores
Traffic hotspots, a severe form of network congestion, can be caused unexpectedly in a
network-on-chip (NoC) due to the immanent spatio-temporal unevenness of application …
network-on-chip (NoC) due to the immanent spatio-temporal unevenness of application …
Quadrant-based XYZ dimension order routing algorithm for 3-D Asymmetric Torus Routing Chip (ATRC)
The conventional two-dimensional (2-D) integrated circuit (IC) has limited scope for floor
planning and therefore limits the performance improvements resulting from the Network-on …
planning and therefore limits the performance improvements resulting from the Network-on …
A Markovian performance model for networks-on-chip
Network-on-chip (NoC) has been proposed as a solution for addressing the design
challenges of future high-performance nanoscale architectures. Thus, it is of crucial …
challenges of future high-performance nanoscale architectures. Thus, it is of crucial …
n-Bit multiple read and write FIFO memory model for network-on-chip
Network-on-chip (NoC) architecture provides the communication infrastructure for system-on-
chip (SoC) design. The architecture, size, and algorithm dominate the performance of NoC …
chip (SoC) design. The architecture, size, and algorithm dominate the performance of NoC …
An iterative computational technique for performance evaluation of networks-on-chip
The trend toward integrated many-core architectures makes the network-on-chip (NoC)
technology, the on-chip communication infrastructure of choice. However, and as opposed …
technology, the on-chip communication infrastructure of choice. However, and as opposed …
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
M Arjomand, H Sarbazi-Azad - IEEE Transactions on Computer …, 2010 - ieeexplore.ieee.org
End-to-end delay, throughput, energy consumption, and silicon area are the most important
design metrics of networks-on-chip (NoCs). Although several analytical models have been …
design metrics of networks-on-chip (NoCs). Although several analytical models have been …
HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips
The inherent spatio-temporal unevenness of traffic flows in Networks-on-Chips (NoCs) can
cause unforeseen, and in cases, severe forms of congestion, known as hotspots. Hotspots …
cause unforeseen, and in cases, severe forms of congestion, known as hotspots. Hotspots …
Design and analysis of static memory management policies for CC-NUMA multiprocessors
In this paper, we characterize the performance of three existing memory management
techniques, namely, buddy, round-robin, and first-touch policies. With existing memory …
techniques, namely, buddy, round-robin, and first-touch policies. With existing memory …
A parameterized NoC simulator using OMNet++
R Al-Badi, M Al-Riyami, N Alzeidi - … International Conference on …, 2009 - ieeexplore.ieee.org
Wormhole switching with virtual channels has been widely deployed in high-speed
interconnects at different scales. Its minimal buffer requirements and simple router design …
interconnects at different scales. Its minimal buffer requirements and simple router design …