Automatic generation of architecture-level models from RTL designs for processors and accelerators
Hardware platforms comprise general-purpose processors and application-specific
accelerators. Unlike processors, application-specific accelerators often do not have clearly …
accelerators. Unlike processors, application-specific accelerators often do not have clearly …
Holistic development of computer engineering curricula using Y-chart methodology
<? Pub Dtl=""?> The exponential growth of advancing technologies is pushing curriculum
designers in computer engineering (CpE) education to compress more and more content …
designers in computer engineering (CpE) education to compress more and more content …
Generating architecture-level abstractions from RTL designs for processors and accelerators part i: Determining architectural state variables
Today's Systems-on-Chips (SoCs) comprise general/special purpose programmable
processors and specialized hardware modules referred to as accelerators. These …
processors and specialized hardware modules referred to as accelerators. These …
A layered methodology for the simulation of extra-functional properties in smart systems
Smart systems represent a broad class of intelligent, miniaturized devices incorporating
functionality like sensing, actuation, and control. In order to support these functions, they …
functionality like sensing, actuation, and control. In order to support these functions, they …
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
K Grüttner, R Görgen, S Schreiner, F Herrera… - Microprocessors and …, 2017 - Elsevier
The increasing processing power of today's HW/SW platforms leads to the integration of
more and more functions in a single device. Additional design challenges arise when these …
more and more functions in a single device. Additional design challenges arise when these …
Event recognition based on deep learning in Chinese texts
Y Zhang, Z Liu, W Zhou… - PloS one, 2016 - journals.plos.org
Event recognition is the most fundamental and critical task in event-based natural language
processing systems. Existing event recognition methods based on rules and shallow neural …
processing systems. Existing event recognition methods based on rules and shallow neural …
Reusing RTL assertion checkers for verification of SystemC TLM models
The recent trend towards system-level design gives rise to new challenges for reusing
existing (RTL) intellectual properties (IPs) and their verification environment in (TLM). While …
existing (RTL) intellectual properties (IPs) and their verification environment in (TLM). While …
Accelerating RTL fault simulation through RTL-to-TLM abstraction
Different fault injection techniques based on simulation have been proposed in the past for
functional verification of register transfer level (RTL) IP models. They allow designers to …
functional verification of register transfer level (RTL) IP models. They allow designers to …
ONTO-PLC: An ontology-driven methodology for converting PLC industrial plants to IoT
We present the new methodology ONTO-PLC to deliver software programs on system-on-
chip or single-board computers used to control industrial plants, as substitutes for …
chip or single-board computers used to control industrial plants, as substitutes for …
Automatic refinement of requirements for verification throughout the SoC design flow
L Pierre, ZBH Amor - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
This paper focuses on the verification of requirements for hardware/software systems on
chip (SoC's) along the design flow. In the early stages of this flow, the Electronic System …
chip (SoC's) along the design flow. In the early stages of this flow, the Electronic System …