This paper extends the CMOS standard cells characterization methodology for defect based
testing. The proposed methodology allows to find the types of faults which may occur in a …

The complexity of Networks-on-Chip (NoC) makes the application of traditional test methods
obsolete. For NoC, a combination of methods known from the System-on-Chip, memory and …

BDDs have become the state-of-the-art data structure in VLSI CAD. In this paper, a special
class of BDDs is presented called Structurally Synthesized BDDs (SSBDD). The idea of …

A method is proposed for combinational deterministic test pattern generation using a uniform
functional fault model for combinational circuits. This includes an approach, which allows to …

This work shows a new concept to extend the hierarchical approach of standard-cell circuit
design into the area of defect-oriented test pattern generation. For this purpose test patterns …

The development of special software tool named FIESTA (Faults Identification and
Estimation of Test Ability) for the defect/fault analysis in the complex gates from industrial cell …

We address in this paper the defect modeling and testing of intra-cell bridging defects from
the layout perspective. For defect modeling, we incorporate a butterfly structure to resolve …

To cope with the soft errors and make full use of the multi-core system, this paper gives an
efficient fault-tolerant hardware and software co-designed architecture for multi-core …

Due to continuous improvements of semiconductor technologies new challenges for the
design of highly integrated system-on-chip (SoC) solutions have arisen. Systems-on-Chip …

A method is presented for deterministic test pattern generation using a uniform functional
fault model for combinational circuits. The fault model allows to represent the physical …