Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations
An embodiment may comprise memory with a memory array, a resistor coupled to a
reference Voltage, on die termination circuitry coupled with the resistor, and an input …
reference Voltage, on die termination circuitry coupled with the resistor, and an input …
Gallery of messages from individuals with a shared interest
T Sehn - US Patent 11,372,608, 2022 - Google Patents
A machine includes a processor and a memory connected to the processor. The memory
stores instructions executed by the processor to receive a message and a message …
stores instructions executed by the processor to receive a message and a message …
Programmable series on-chip termination impedance and impedance matching
JH Bui, J Costello, S Tran - US Patent 6,836,144, 2004 - Google Patents
Circuits may provide Series on-chip termination impedance to one or more input/output pins.
In one embodiment, two off-chip reference resistors in combination with internal calibration …
In one embodiment, two off-chip reference resistors in combination with internal calibration …
Amplitude calibration element for an enhanced data rates for GSM evolution (EDGE) polar loop transmitter
An amplitude calibration element comprises a linear driver configured to receive the output
of a modulator, the modulator output comprising a Voltage signal having an amplitude …
of a modulator, the modulator output comprising a Voltage signal having an amplitude …
Automated management of ephemeral message collections
N Allen, D Giovannini, C Lin, R Murphy… - US Patent …, 2024 - Google Patents
(57) ABSTRACT A server has a processor and a memory storing instructions executed by
the processor to maintain an ephemeral gallery of ephemeral messages. An ephemeral …
the processor to maintain an ephemeral gallery of ephemeral messages. An ephemeral …
Techniques for calibrating on-chip termination impedances
KW Wei - US Patent 7,372,295, 2008 - Google Patents
A calibration circuit block includes a first resistor network, a second resistor network, and a
feedback loop. The first resistor network includes a set of transistors and receives a constant …
feedback loop. The first resistor network includes a set of transistors and receives a constant …
Techniques for providing calibrated parallel on-chip termination impedance
V Santurkar, H Yi - US Patent 7,443,193, 2008 - Google Patents
Techniques are provided for calibrating parallel on-chip ter mination (OCT) impedance
circuits. An on-chip termination 5,559,448 A 9/1996 Koenig(OCT) calibration circuit …
circuits. An on-chip termination 5,559,448 A 9/1996 Koenig(OCT) calibration circuit …
Geo-location based event gallery
NR Allen, RC Murphy, E Spiegel - US Patent 11,317,240, 2022 - Google Patents
Abstract Systems and methods are provided for determining that geolocation data from a
computing device corresponds to a geo-fence associated with a plurality of galleries and …
computing device corresponds to a geo-fence associated with a plurality of galleries and …
On-chip termination with calibrated driver strength
X Wang, TC Chang, C Sung, KQ Nguyen - US Patent 7,221,193, 2007 - Google Patents
Techniques are provided for controlling an on-chip termi nation resistance in an input or
output (10) buiTer using calibration circuits. Each calibration circuit monitors the voltage …
output (10) buiTer using calibration circuits. Each calibration circuit monitors the voltage …
Programmable termination with DC voltage level control
S Shumarayev, T White - US Patent 7,109,744, 2006 - Google Patents
4,719,369 A 1, 1988 Asano et al. 4.954, 729 A 9/1990 Urai 5,111,081. A 5/1992 Atallah
5,134.311 A 7/1992 Biber et al. 5,151,611 A 9/1992 Rippey 5,164,663 A 1 1/1992 Alcorn …
5,134.311 A 7/1992 Biber et al. 5,151,611 A 9/1992 Rippey 5,164,663 A 1 1/1992 Alcorn …