Optimizing bloom filter: Challenges, solutions, and comparisons

L Luo, D Guo, RTB Ma… - … Surveys & Tutorials, 2018 - ieeexplore.ieee.org
Bloom filter (BF) has been widely used to support membership query, ie, to judge whether a
given element x is a member of a given set S or not. Recent years have seen a flourish …

Managing cache coherency in a data processing apparatus

E Özer, SD Biles, SA Ford - US Patent 7,937,535, 2011 - Google Patents
US PATENT DOCUMENTS 6,272.520 B1 8/2001 Sharangpani et al. 6,338,123 B2* 1/2002
Joseph et al.................. 711/144 6,704,845 B2* 3/2004 Anderson et al.............. 711.146 …

Energy management for commercial servers

C Lefurgy, K Rajamani, F Rawson, W Felter… - Computer, 2003 - ieeexplore.ieee.org
Servers: high-end, multiprocessor systems running commercial workloads, have typically
included extensive cooling systems and resided in custom-built rooms for high-power …

Efficiently enabling conventional block sizes for very large die-stacked DRAM caches

GH Loh, MD Hill - Proceedings of the 44th Annual IEEE/ACM …, 2011 - dl.acm.org
Die-stacking technology enables multiple layers of DRAM to be integrated with multicore
processors. A promising use of stacked DRAM is as a cache, since its capacity is insufficient …

[BUKU][B] Multiprocessor systems-on-chips

A Jerraya, W Wolf - 2004 - books.google.com
Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

Scale-out processors

P Lotfi-Kamran, B Grot, M Ferdman, S Volos… - ACM SIGARCH …, 2012 - dl.acm.org
Scale-out datacenters mandate high per-server throughput to get the maximum benefit from
the large TCO investment. Emerging applications (eg, data serving and web search) that run …

LogTM-SE: Decoupling hardware transactional memory from caches

L Yen, J Bobba, MR Marty, KE Moore… - 2007 IEEE 13th …, 2007 - ieeexplore.ieee.org
This paper proposes a hardware transactional memory (HTM) system called LogTM
Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transactions read …

Heterogeneous system coherence for integrated CPU-GPU systems

J Power, A Basu, J Gu, S Puthoor… - Proceedings of the 46th …, 2013 - dl.acm.org
Many future heterogeneous systems will integrate CPUs and GPUs physically on a single
chip and logically connect them via shared memory to avoid explicit data copying. Making …

[BUKU][B] Computer architecture techniques for power-efficiency

S Kaxiras, M Martonosi - 2008 - books.google.com
In the last few years, power dissipation has become an important design constraint, on par
with performance, in the design of new computer systems. Whereas in the past, the primary …

Dynamic power-performance adaptation of parallel computation on chip multiprocessors

J Li, JF Martinez - The Twelfth International Symposium on …, 2006 - ieeexplore.ieee.org
Previous proposals for power-aware thread-level parallelism on chip multiprocessors
(CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of …