An ultra-low-power fully-static contention-free flip-flop with complete redundant clock transition and transistor elimination
A redundancy eliminated flip-flop (REFF) is proposed targeting wide-range voltage
scalability (1–0.3 V). Two types of redundancies are eliminated in the REFF to achieve low …
scalability (1–0.3 V). Two types of redundancies are eliminated in the REFF to achieve low …
A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS
J Li, A Chang, TTH Kim - IEEE Journal of Solid-State Circuits, 2018 - ieeexplore.ieee.org
This paper presents an extremely low-voltage and low-power single-phase-clocking
redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a …
redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a …
A differential flip-flop with static contention-free characteristics in 28 nm for low-voltage, low-power applications
G Shin, E Lee, J Lee, Y Lee… - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
A static contention-free differential flip-flop (SCDFF) is presented in 28-nm CMOS for low-
voltage and low-power applications. The SCDFF offers fully static and contention-free …
voltage and low-power applications. The SCDFF offers fully static and contention-free …
Design of a dual change-sensing 24t flip-flop in 65 nm cmos technology for ultra low-power system chips
In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual
change-sensing scheme is discussed. Further, in order to reduce power consumption, a new …
change-sensing scheme is discussed. Further, in order to reduce power consumption, a new …
Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design
JF Lin, ZJ Hong, JT Wu, XY Tung, CH Yang, YC Yen - Sensors, 2022 - mdpi.com
A low-voltage and low-power true single-phase flip-flop that minimum the total transistor
count by using the pass transistor logic circuit scheme is proposed in this paper …
count by using the pass transistor logic circuit scheme is proposed in this paper …
A Power-Efficient 10T D Flip-Flop with Dual Line of Four Switches using 65nm CMOS Technology
E Lee, Y Kim - 2023 20th International SoC Design Conference …, 2023 - ieeexplore.ieee.org
D flip-flops play a critical role as components in digital circuits, providing the ability to store
data and ensure synchronization. In the realm of AI and modern digital electronics, the …
data and ensure synchronization. In the realm of AI and modern digital electronics, the …
Low Power Flip-Flop Circuit with a Minimization of Internal Node Transition
H Choi, S Yun, S Kim, M Song - Transactions on Semiconductor …, 2023 - koreascience.kr
This paper presents a low-power flip-flop (FF) circuit that minimizes the transition of internal
nodes by using a dual change-sensing method. The proposed dual change-sensing FF …
nodes by using a dual change-sensing method. The proposed dual change-sensing FF …
Ultra-low power digital integrated circuit design
VL Le - 2019 - dr.ntu.edu.sg
Relentless advancement of process technology has tremendously brought massive
performance boosts and much more integration to modern digital circuits and systems …
performance boosts and much more integration to modern digital circuits and systems …