Optimization of electrical properties in TiO2/WSix-based vertical DG-MOSFET using Taguchi-based GRA with ANN

KE Kaharudin, F Salehuddin… - … , Electronic and Computer …, 2018 - jtec.utem.edu.my
This study describes a proposed method to determine the most optimal level of process
parameters, considering multiple electrical properties of titanium dioxide/tungsten silicide …

Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array

F Salehuddin, I Ahmad, FA Hamid… - 2012 10th IEEE …, 2012 - ieeexplore.ieee.org
In this study, orthogonal array of L 18 in Taguchi method was used to optimize the process
parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide …

Cobalt silicide and titanium silicide effects on nano devices

HA Elgomati, BY Majlis, F Salehuddin… - 2011 IEEE Regional …, 2011 - ieeexplore.ieee.org
This paper describes growth process of the two silicide Sub-nanometer devices and the
different effects of having cobalt silicide and titanium silicide on a Sub-nanometer CMOS …

Analysis of process parameter effect on DIBL in n-channel MOSFET device using L27 orthogonal array

F Salehuddin, KE Kaharudin, ASM Zain… - AIP Conference …, 2014 - pubs.aip.org
In this research, the effect of the process parameters variation on drain induced barrier
lowering (DIBL) was investigated. The fabrication of the transistor device was performed …

Modeling and optimization of GAAFET transistor using Taguchi approach and artificial neural network (ANN)

N Al Harbi, M Belkhiria… - 2023 IEEE international …, 2023 - ieeexplore.ieee.org
In this work, a gate all around GAAFET transistor has been studied and numerically
optimized. The finite element method was adopted for the discretization of the equations …

Design of 6T SRAM Cell Using Optimized 20 nm SOI Junctionless Transistor

MFM Noor, NE Alias, A Hamzah… - 2019 IEEE Regional …, 2019 - ieeexplore.ieee.org
The semiconductor industry has shifted to the System-On-Chip (SoC) platform. The short
channel effects (SCEs) turns out to be noticeable with the transistor scaling. Consequently …

Design and optimization of TiSix/HfO2 channel vertical double gate NMOS device

KE Kaharudin, F Salehuddin, ASM Zain… - 2016 IEEE …, 2016 - ieeexplore.ieee.org
This paper aims to propose a new structure of vertical double-gate NMOS device with
titanium silicide (TiSi x) and hafnium dioxide (HfO 2) are utilized as gates and an insulator …

Design and optimization of a Mach-Zehnder Interferometer (MZI) for optical modulators

HA Razak, H Haroon, PS Menon… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
This paper presents an investigation of the most influential parameters in designing a Mach
Zehnder Interferometer (MZI) on Silicon-On-Insulator (SOI) using Taguchi method. The …

Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET

F Salehuddin, I Ahmad, FA Hamid… - 2011 IEEE Regional …, 2011 - ieeexplore.ieee.org
In this paper, Taguchi method was used to analyze of input process parameters variations
on threshold voltage (V TH) in 45nm n-channel Metal Oxide Semiconductor device. The …

Designing asymmetric 2.4 ghz rf oscillator for improving signal integrity by design of experiments

JN Tripathi, J Mukherjee… - 2010 IEEE Asia Pacific …, 2010 - ieeexplore.ieee.org
Designing of an Asymmetric RF Oscillator for improved Signal Integrity, using Design of
Experiments is presented and Taguchi Orthogonal Array is used for the same. Dependence …