As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis
becomes even more challenging. Modern VLSI interconnects are more resistive, signals no …

With process technology scaling, accurate gate-level timing analysis becomes even more
challenging. Highly resistive on-chip interconnects have an ever-increasing impact on …

In recent years, physical unclonable functions (PUFs) have gained a lot of attention as
mechanisms for hardware-rooted device authentication. While the majority of the previously …

Aggressive technology scaling and increased static and dynamic variability caused by
process, temperature, voltage, and aging effects make nanometer circuits prone to timing …

As the transistor shrinks to nanoscale, the overhead of ensuring circuit functionality becomes
extremely large due to the increasing timing variations. Thus, better-than-worst-case design …

The susceptibility of Integrated Circuits (ICs) to soft errors has always been a major concern.
However, the shrinking of CMOS technology nodes, which results in high frequency, low …

The incessant decrease in transistor size has led to reduced voltage noise margins and
exacerbated power integrity challenges. This trend intensifies concerns about the efficacy of …

Multiple Input Switching (MIS) effects commonly induce undesired glitch pulses at the output
of CMOS gates, potentially leading to circuit malfunction and significant power consumption …

Nanometer circuits are becoming increasingly prone to timing errors due to worsening
parametric variations and operation close to voltage and frequency limits. Such errors …

Radiation-induced soft errors in Integrated Circuits (ICs) have always been a matter of great
reliability concern. However, the ongoing shrinking of CMOS technology nodes, which …